Index
Analog design
breaker cell
ESD design
floorplanning
guard rings
I/O
layout
mixed signal
peripheral I/O
Application specific integrated circuits (ASICs)
array I/O Design
breaker cell
ESD design
floorplanning
guard rings
I/O
layout
mixed signal
peripheral I/O
Architecture
array I/O
bottom-up design
DRAM
floorplanning
I/O
image processing semiconductor chips
layout
microprocessors
mixed signal
mixed voltage
peripheral I/O
SRAM
top-down design
Avalanche
avalanche breakdown
avalanche multiplication
Bipolar transistors
parasitic bipolar transistors
silicon
Bond pad
ESD adjacent to bond pad
ESD under bond pad
octagonal bond pad
radio frequency (RF) bond pads
rectangular bond pad
split ESD design
split I/O design
Bottom-up design
ESD power clamp placement
ESD power clamps
ESD signal pins
ground bus
power bus
Bus
Across-ESD bus resistance
clamp-to-clamp resistance
ESD dummy bus
ground bus
power bus
Cable discharge event (CDE)
ESD networks
latchup
pulse waveform
waveform
Charged board model
test
verification
waveform
Charged device model (CDM)
characterization method
ESD signal pin protection networks
failure criteria
failure mechanisms
Deep trench
bipolar transistors
ESD structures
guard ring structures
latchup
polysilicon filled deep trench structures
Degradation
alternating current (a.c.)
direct current (d.c.)
leakage
radio frequency (RF)
Design synthesis
ESD power clamp
ESD signal pin
ground bus
ground power rail
power rail
Dielectrics
buried oxide (BOX)
inter-level dielectric ...
