Chapter 5
ESD Signal Pin Networks Design and Synthesis
5.1 ESD Signal Pin Structures
In this chapter, ESD signal pin networks will be explored. Today, it is common practice to have ESD networks on all signal pins and they form a critical part of the ESD design synthesis [1–39]. Development of ESD signal pin networks and synthesis into the semiconductor chip architecture is part of the ESD design discipline and an essential component of the art of ESD design. Due to the wealth of material on this subject, the focus will instead be on the integration, design synthesis, key parameters, and layout, as opposed to discussing all forms of ESD input circuitry. First, the focus of the chapter will address integration of the ESD signal pin with the bond pad. This will be followed by discussion of MOSFET layout design [1–3, 13–16], diode layout [1–3, 8–21], SCR design [3, 6, 13–16], as well as passive elements (resistors and inductors) [5, 6]. Examples will be addressed from CMOS digital [1–21], analog [6], and RF applications [4, 5, 27–38].
Today, it is common practice to have ESD networks on all signal pins. Typically, the only cases that do not require ESD networks are “self-protecting networks.” ESD signal pin structures are a critical part of the ESD design synthesis. In the following sections, active and passive elements used in ESD protection circuits will be discussed. In the discussion, the characteristics, design practices, and physical layout will be highlighted. As this subject ...
