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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 18

RELEASING AND SUPPORTING

18.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

“There is never time to do it right, but there is always time to do it over.” This old truism in the integrated circuit design world applies more to actual design of integrated circuits than to stdcell library development. At deeper submicron technology nodes, although it remains possible in terms of both time and resource to always “do it over,” the shear cost of even a single mask makes a mistake virtually too expensive to recover from. In the future, do not be amazed that only the highest volume devices will “fix” poor design whereas other “mistakes” are either resolved by a software fix or by removal of the proposed feature for the marketing of the device. The truism for stdcells is more along the lines of “It has to be done right, and it has to be done now.”

A couple of years ago, I was working in a digital design center, supporting its foundation intellectual property (IP). That foundation IP, which included external vendor devices of various types, included internally developed stdcells from another central library organization. The stdcell library for one of those technology nodes was optimized for density “at all cost.” That library, among other issues, had removed the output buffers from the latch sequential cells (in order to remove as much added area as possible from the resulting placements). Figure 18.1 gives the basic circuit of these unbuffered ...

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