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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 17

TAGGING AND REVISIONING

17.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

Several years ago, I was supporting a 90-nanometer stdcell library that I had created. That particular library had been given to several companies because of some consortiums. The technology node that the library was based on had a minimum metal area rule in it. This was the first technology node where such design rule check (DRC) issues had existed. The automatic place and route tools available at the time could not handle such issues; the library exchange format (LEF) had to ensure that such minimum metal area issues could not occur during place and route “by construction.” That particular minimum metal area rule was sufficiently large that the middle metals in any stacked VIA construct would have to encroach on one or more of the surrounding router tracks on whatever particular metal happened to be the sandwiched layer of the stacked VIA. If the area was grown sufficiently large for the rule and done so in a symmetrical fashion, then it would encroach on all four surrounding router grids.

Because stacked VIA were desirable by the design teams that were using the library, I experimented with drawing four separate versions of oblong versions of the minimum area and placing them in the part of the physical LEF file that was used to define VIA constructs. The hope was that the router that was then used would choose from the four stacked VIA constructs such ...

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