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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 16

PLAYING WITH THE PHYSICAL DESIGN KIT: USUALLY “AT YOUR OWN RISK”

16.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

At the microprocessor company where I was employed when I built the 90-nanometer stdcell library, the manufacturing grid that was chosen for development of that library was 5 nanometers. However, every minimum design rule check (DRC)—in terms of spacing, overhang, and width—was a multiple of 10 nanometers. This may, at first, seem slightly strange. Why build a manufacturing grid that is twice the refinement (half the granularity) of any geometry that can be built with it? Actually, that is a slight overstatement. The minimum DRC rules were all multiples of 10 nanometers, but there was no restriction on building features that were an odd number of multiples of the manufacturing grid larger longer or wider than the minimum. In addition, for design for manufacturing (DFM), this is exactly what we did. (Please refer to the discussion in Chapter 14 about lessons learned on such DFM extensions, and what they mean in terms of yield.) However, 5 nanometers is a very tiny level of granulation. At such a level, a physical layout engineer is viewing a layout at a level of magnification only slightly larger than what would be sufficient so that full DRC rules (in terms of widths or spaces or overlaps) can be seen. The slight change in a shape because one corner of the polygon being shifted one 5-nanometer grid becomes nearly ...

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