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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 14

DESIGN FOR MANUFACTURABILITY

14.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

It has been claimed that the best design for manufacturability (DFM) for any given structure to be processed at a given technology node is to draw that structure using the design rules for the next higher technology node. Actually, this is a slight overstatement. It is commonly held that a rough estimate would be that 90% of the benefit, in terms of yield improvement, that can be accomplished for deep submicron design can be had by increasing the width or space or overlap rule in question by one manufacturing grid beyond the design rule check (DRC) rule. This yield-improvement trend continues for each succeeding manufacturing-grid increase—that is, a second manufacturing-grid increase would gain an additional 90% of the remaining 10% yield loss for 99% total gain in yield improvement. A third grid increase captures another 90% of the remaining 1% yield loss not otherwise captured, or a total of 99.9%, which is beyond the normal 3-sigma range that typical modern integrated circuit (IC) devices are designed toward. Table 14.1 roughly enumerates this.

TABLE 14.1 Yield Benefit as a Function of Design for Manufacturability. Drawing polygons bigger than minimum increases yield but at a loss of density or performance or both.

Margin Result
Match DRC Set Yield Loss of X%
DRC + 1 Manufacturing Grid Yield Loss of .1*X%
DRC + 2 Manufacturing Grid Yield ...

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