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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 12

TEST VIEWS

12.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

Some of my background has been in the IP development and support of communication-channel designs. One such particular effort more than 15 year ago was for a semicustom clock and data-recovery device implemented in 0.8-micron technology. The device’s communication protocol was to function embedded in the clock within the data stream. The data algorithm ensured that a clock-induced data edge would be forced to present at least once every byte-worth of serial data. By monitoring when these edges occurred, one could surmise when the clock and adjust the internal to the device clock in order to align with the assumed clock of the generating device of the data stream.

There were three complicating factors in this design. One was that in order to achieve the bit error rate that was required, the data stream would have to oversample the data stream by a factor of at least 10. This pushed the technology node capabilities, at least for typical synthesized stdcells. Second, the data stream was noisy. Hence, the exact location of the edges as they crossed threshold from a logical low to a logical high and vice versa was jittery. Third, because of the otherwise unknown time of the guaranteed edge in the data stream, the sampling flops in general needed to be highly tolerant of metastability.

The eventual solution was a semicustom placement and hand routing of stdcells in that technology ...

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