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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 10

NOISE VIEWS

10.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

Pulses die out. In the 1980s and 1990s, that was the mantra of system-on-a-chip (SOC) designs, at least when it came to electromigration (EM) calculations. The capacitive load on a signal was thought to have a sufficiently dampening effect on glitches that combinations of short-path and long-path minterms within a complex cone of logic would not cause considerable toggling of the various signals within itself that might otherwise force EM considerations on the signal. Figure 10.1 shows a worst-case parity-tree example. If all of the inputs to such a tree change at the same time, each signal (with a different delay to the output if the loading was not present) could cause the last stage to toggle up or down before finally settling back to the original state of the output. However, because there was such a load on the various signals, any glitch on an output of a XOR in the tree would tend not to reach a voltage level sufficient to change the next stage within the tree. Back in the 1980s and 1990s, before signal-integrity failures started to occur with much frequency, this was usually not questioned (or checked). Although the preceding analysis was for EM, back in the 1980s and 1990s it also held for noise. Any aggressor net-induced pulse on a victim net would tend to die out as well. For years, typical SOC design engineers did not bother with calculating noise immunity ...

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