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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 8

TIMING VIEWS

8.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

Early in my career, I was working for a defense contractor. We were doing a series of 25-MHz CMOS designs. Even as a junior-level engineer, I was put in charge of an entire memory map unit design. This was a large design by the standards of the time, perhaps 20,000 gates. I was proud. After I had the circuit designed and properly simulating and had completed initial placement and routing of the function, I commenced timing closure of the circuit, which was very rudimentary at the time. We could go in and substitute higher drive strength cells for lower drive strength cells, and we could move some placement and some routing, but modern-day tools such as those allowing useful skew had not yet been developed. The short paths were resolved quickly, a tribute, as I saw it, to my foresight during the circuit design. The long paths took a little longer, and even though there were not too many, I struggled. Finally, after several weeks, whereas some of the other designers had already released their chips to processing, I was down to one remaining long path. It was less than 40.1 nanoseconds long, including propagation, setup, and clock skew, and I could not figure out a way to get those last 100 pico-seconds out of the design. I worked at it day and night for two weeks and nothing I tried would reduce that last long path, Finally, one Friday morning, I went in to my boss’s office ...

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