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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 7

SPICE

7.1 LESSON FROM THE REAL WORLD: THE MANAGER’S PERSPECTIVE AND THE ENGINEER’S PERSPECTIVE

In the mid-1990s, I was asked to develop a 350-nanometer universal serial bus (USB) 1.0 input–output (IO) to support the addition of such a communication channel onto a series of parts. USB IO development is simple and straightforward, at least for the revision 1.0 specification, which is available from the USB consortium at usb.org. Two current-voltage (I-V) waveform envelopes define the loaded IO outputs. These were defined in such a manner as to allow any vendor’s CMOS process to be capable of doing so with appropriately sized IO totem-pole P-channel and N-channel transistors. Even the rise-time and fall-time slope requirements introduced in revision 1.1 were not difficult additions to include. The only real issue was the need for a “hot plug” that allowed the IO to be powered for as long as a day with the chip itself remaining unpowered without damaging the device. We solved this through some isolation techniques on the IO power and IO substrate connections. However, when the register-transfer language (RTL) designers attempted actually to integrate the IO while designing the USB channel, they found that the synthesis through the IO and cone of logic to the first FLIP-FLOPs, internal, and the reverse of this path—that is, FLIP-FLOP, cone of logic, and IO—was longer than the specification could handle. Because the IO was new and had not seen silicon before, it became the ...

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