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Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon by DAVID DOMAN

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CHAPTER 2

STDCELL LIBRARIES

2.1 LESSON FROM THE REAL WORLD: MANAGER’S PERSPECTIVE AND ENGINEER’S PERSPECTIVE

Back when all logic design was accomplished by generating hand-designed schematics, it used to be said that once you became familiar enough with a certain logic designer’s style, you could tell which schematics where done by that person versus which were done by other logic designers. In effect, just as is the case with classical painters and their paintings, each designer had a brush stroke that was all his or her own. Each logic designer was an artist in the field of logic design, admittedly some more than others.

Although the ability to see this artistry in an Register Transfer Language (RTL) netlist might be lessened because of the structural requirements of the RTL combined with the design-center restrictions on techniques, it is still sometimes observable in the resultant synthesized netlist that came from the original RTL. A netlist from some designers will have a different ratio of inverters to flip-flops or a different mix of Boolean functions or any of a number of other telltale fingerprints that would allow the seasoned observer to say one netlist was produced by one logic designer while somebody else produced another—that is, if the stdcell library is rich enough to allow such subtleties to arise.

A couple of years ago, a design center asked why I produced such large stdcell libraries. Typically, that design center would purchase a 350–450 cell library and be ...

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