You are previewing Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon.
O'Reilly logo
Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon

Book Description

Shows readers how to gain the competitive edge in the integrated circuit marketplace

This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.

Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn:

  • How to work with overdesigned std-cell libraries to improve profitability while maintaining safety

  • How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions

  • How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor

  • How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views

  • How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design

Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.

Table of Contents

  1. Cover
  2. Contents
  3. Title
  4. Copyright
  5. Preface
  6. Acknowledgments
  7. Chapter 1: Introduction
    1. 1.1 Adding Project-Specific Functions, Drive Strengths, Views, and Corners
    2. 1.2 What Is a DDK?
  8. Chapter 2: Stdcell Libraries
    1. 2.1 Lesson from the Real World: Manager’s Perspective and Engineer’s Perspective
    2. 2.2 What Is a Stdcell?
    3. 2.3 Extended Library Offerings
    4. 2.4 Boutique Library Offerings
    5. 2.5 Concepts for Further Study
  9. Chapter 3: IO Libraries
    1. 3.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 3.2 Extension Capable Architectures versus Function Complete Architectures
    3. 3.3 Electrostatic Discharge Considerations
    4. 3.4 Concepts for Further Study
  10. Chapter 4: Memory Compilers
    1. 4.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 4.2 Single Ports, Dual Ports, and ROM: The Compiler
    3. 4.3 Nonvolatile Memories: The Block
    4. 4.4 Special-Purpose Memories: The Custom
    5. 4.5 Concepts for Further Study
  11. Chapter 5: Other Functions
    1. 5.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 5.2 Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs
    3. 5.3 Low-Power Support Structures
    4. 5.4 Stitching Structures
    5. 5.5 Hard, Firm, and Soft Boxes
    6. 5.6 Concepts for Further Study
  12. Chapter 6: Physical Views
    1. 6.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 6.2 Picking an Architecture
    3. 6.3 Measuring Density
    4. 6.4 The Need and the Way to Work with Fabrication Houses
    5. 6.5 Concepts for Further Study
  13. Chapter 7: SPICE
    1. 7.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 7.2 Why a Tool More Than 40 Years Old Is Still Useful
    3. 7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye
    4. 7.4 Sufficient Parasitics
    5. 7.5 Concepts for Further Study
  14. Chapter 8: Timing Views
    1. 8.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 8.2 Performance Limits and Measurement
    3. 8.3 Default Versus Conditional Arcs
    4. 8.4 Break-Point Optimization
    5. 8.5 A Word on Setup and Hold
    6. 8.6 Failure Mechanisms and Roll-Off
    7. 8.7 Supporting Efficient Synthesis
    8. 8.8 Supporting Efficient Timing Closure
    9. 8.9 Design Corner Specific Timing Views
    10. 8.10 Nonlinear Timing Views are so “Old Hat” . . .
    11. 8.11 Concepts for Further Study
  15. Chapter 9: Power Views
    1. 9.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 9.2 Timing Arcs Versus Power Arcs
    3. 9.3 Static Power
    4. 9.4 Real Versus Measured Dynamic Power
    5. 9.5 Should Power Be Built as a Monotonic Array?
    6. 9.6 Best-Case and Worst-Case Power Views Versus Best-Case and Worst-Case Timing Views
    7. 9.7 Efficiently Measuring Power
    8. 9.8 Concepts for Further Study
  16. Chapter 10: Noise Views
    1. 10.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 10.2 Noise Arcs Versus Timing and Power Arcs
    3. 10.3 The Easy Part
    4. 10.4 The Not-So-Easy Part
    5. 10.5 Concepts for Further Study
  17. Chapter 11: Logical Views
    1. 11.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 11.2 Consistency Across Simulators
    3. 11.3 Consistency with Timing, Power & Noise Views
    4. 11.4 Concepts for Further Study
  18. Chapter 12: Test Views
    1. 12.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 12.2 Supporting Reachability
    3. 12.3 Supporting Observability
    4. 12.4 Concepts for Further Study
  19. Chapter 13: Consistency
    1. 13.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 13.2 Validating Views across a Library
    3. 13.3 Validating Stdcells across a Technology Node
    4. 13.4 Validating Libraries across Multiple Technology Nodes
    5. 13.5 Concepts for Further Study
  20. Chapter 14: Design for Manufacturability
    1. 14.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 14.2 What is DFM?
    3. 14.3 Concepts for Further Study
  21. Chapter 15: Validation
    1. 15.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 15.2 Quality Levels
    3. 15.3 Concepts for Further Study
  22. Chapter 16: Playing with the Physical Design Kit: Usually “At Your Own Risk”
    1. 16.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 16.2 Manipulating Models
    3. 16.3 Added Unsupported Devices
    4. 16.4 Concepts for Further Study
  23. Chapter 17: Tagging and Revisioning
    1. 17.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 17.2 Tagging and Time Stamps
    3. 17.3 Metadata, Directory Structures, and Pointers
    4. 17.4 Concepts for Further Study
  24. Chapter 18: Releasing and Supporting
    1. 18.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 18.2 When Is Test Silicon Needed for Verification?
    3. 18.3 Sending the Baby Out the Door
    4. 18.4 Multiple Quality Levels on the Same Design
    5. 18.5 Supporting “Bug Fixes”
    6. 18.6 Concepts for Further Study
  25. Chapter 19: Other Topics
    1. 19.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
    2. 19.2 Supporting High-Speed Design
    3. 19.3 Supporting Low-Power Design
    4. 19.4 Supporting Third-Party Libraries
    5. 19.5 Supporting Black Box Third-Party IP (Intellectual Property) Design
    6. 19.6 Supporting Multiple Library Design
    7. 19.7 Concepts for Further Study
  26. Chapter 20: Communications
    1. 20.1 Manager’s Perspective
    2. 20.2 Customer’s Perspective
    3. 20.3 Vendor’s Perspective
    4. 20.4 Engineer’s Perspective
    5. 20.5 Concepts for Further Study
    6. 20.6 Conclusions
  27. Appendix I
  28. Appendix II
  29. Appendix III
  30. Appendix IV
  31. Index