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Embedded Systems: Hardware, Design and Implementation

Book Description

Covers the significant embedded computing technologies—highlighting their applications in wireless communication and computing power

An embedded system is a computer system designed for specific control functions within a larger system—often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. Presented in three parts, Embedded Systems: Hardware, Design, and Implementation provides readers with an immersive introduction to this rapidly growing segment of the computer industry.

Acknowledging the fact that embedded systems control many of today's most common devices such as smart phones, PC tablets, as well as hardware embedded in cars, TVs, and even refrigerators and heating systems, the book starts with a basic introduction to embedded computing systems. It hones in on system-on-a-chip (SoC), multiprocessor system-on-chip (MPSoC), and network-on-chip (NoC). It then covers on-chip integration of software and custom hardware accelerators, as well as fabric flexibility, custom architectures, and the multiple I/O standards that facilitate PCB integration.

Next, it focuses on the technologies associated with embedded computing systems, going over the basics of field-programmable gate array (FPGA), digital signal processing (DSP) and application-specific integrated circuit (ASIC) technology, architectural support for on-chip integration of custom accelerators with processors, and O/S support for these systems.

Finally, it offers full details on architecture, testability, and computer-aided design (CAD) support for embedded systems, soft processors, heterogeneous resources, and on-chip storage before concluding with coverage of software support—in particular, O/S Linux.

Embedded Systems: Hardware, Design, and Implementation is an ideal book for design engineers looking to optimize and reduce the size and cost of embedded system products and increase their reliability and performance.

Table of Contents

  1. Cover
  2. Title page
  3. Copyright page
  4. PREFACE
  5. CONTRIBUTORS
  6. 1 Low Power Multicore Processors for Embedded Systems
    1. 1.1 MULTICORE CHIP WITH HIGHLY EFFICIENT CORES
    2. 1.2 SUPERH™ RISC ENGINE FAMILY (SH) PROCESSOR CORES
    3. 1.3 SH-X: A HIGHLY EFFICIENT CPU CORE
    4. 1.4 SH-X FPU: A HIGHLY EFFICIENT FPU
    5. 1.5 SH-X2: FREQUENCY AND EFFICIENCY ENHANCED CORE
    6. 1.6 SH-X3: MULTICORE ARCHITECTURE EXTENSION
    7. 1.7 SH-X4: ISA AND ADDRESS SPACE EXTENSION
  7. 2 Special-Purpose Hardware for Computational Biology
    1. 2.1 MOLECULAR DYNAMICS SIMULATIONS ON GRAPHICS PROCESSING UNITS
    2. 2.2 SPECIAL-PURPOSE HARDWARE AND NETWORK TOPOLOGIES FOR MD SIMULATIONS
    3. 2.3 QUANTUM MC APPLICATIONS ON FIELD-PROGRAMMABLE GATE ARRAYS
    4. 2.4 CONCLUSIONS AND FUTURE DIRECTIONS
  8. 3 Embedded GPU Design
    1. 3.1 INTRODUCTION
    2. 3.2 SYSTEM ARCHITECTURE
    3. 3.3 GRAPHICS MODULES DESIGN
    4. 3.4 SYSTEM POWER MANAGEMENT
    5. 3.5 IMPLEMENTATION RESULTS
    6. 3.6 CONCLUSION
  9. 4 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors
    1. 4.1 INTRODUCTION
    2. 4.2 THE DVP INTERFACE
    3. 4.3 THE IBRIDGE-BB ARCHITECTURE
    4. 4.4 HARDWARE IMPLEMENTATION
    5. 4.5 CONCLUSION
    6. ACKNOWLEDGMENTS
  10. 5 Embedded Computing Systems on FPGAs
    1. 5.1 FPGA ARCHITECTURE
    2. 5.2 FPGA CONFIGURATION TECHNOLOGY
    3. 5.3 SOFTWARE SUPPORT
    4. 5.4 FINAL SUMMARY OF CHALLENGES AND OPPORTUNITIES FOR EMBEDDED COMPUTING DESIGN ON FPGAS
  11. 6 FPGA-Based Emulation Support for Design Space Exploration
    1. 6.1 INTRODUCTION
    2. 6.2 STATE OF THE ART
    3. 6.3 A TOOL FOR ENERGY-AWARE FPGA-BASED EMULATION: THE MADNESS PROJECT EXPERIENCE
    4. 6.4 ENABLING FPGA-BASED DSE: RUNTIME-RECONFIGURABLE EMULATORS
    5. 6.5 USE CASES
  12. 7 FPGA Coprocessing Solution for Real-Time Protein Identification Using Tandem Mass Spectrometry
    1. 7.1 INTRODUCTION
    2. 7.2 PROTEIN IDENTIFICATION BY SEQUENCE DATABASE SEARCHING USING MS/MS DATA
    3. 7.3 RECONFIGURABLE COMPUTING PLATFORM
    4. 7.4 FPGA IMPLEMENTATION OF THE MS/MS SEARCH ENGINE
    5. 7.5 SUMMARY
    6. ACKNOWLEDGMENTS
  13. 8 Real-Time Configurable Phase-Coherent Pipelines
    1. 8.1 INTRODUCTION AND PURPOSE
    2. 8.2 HISTORY AND RELATED METHODS
    3. 8.3 IMPLEMENTATION FRAMEWORK
    4. 8.4 PROTOTYPE IMPLEMENTATION
    5. 8.5 ASSESSMENT COMPARED WITH RELATED METHODS
  14. 9 Low Overhead Radiation Hardening Techniques for Embedded Architectures
    1. 9.1 INTRODUCTION
    2. 9.2 RECENTLY PROPOSED SEU TOLERANCE TECHNIQUES
    3. 9.3 RADIATION-HARDENED RECONFIGURABLE ARRAY WITH INSTRUCTION ROLLBACK
    4. 9.4 CONCLUSION
  15. 10 Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip
    1. 10.1 INTRODUCTION
    2. 10.2 RELATED WORK
    3. 10.3 PROPOSED 4NP-FIRST ROUTING SCHEME
    4. 10.4 EXPERIMENTS
    5. 10.5 CONCLUSION
  16. 11 Interoperability in Electronic Systems
    1. 11.1 INTEROPERABILITY
    2. 11.2 THE BASIS FOR INTEROPERABILITY: THE OSI MODEL
    3. 11.3 HARDWARE
    4. 11.4 FIRMWARE
    5. 11.5 PARTITIONING THE SYSTEM
    6. 11.6 EXAMPLES OF INTEROPERABLE SYSTEMS
  17. 12 Software Modeling Approaches for Presilicon System Performance Analysis
    1. 12.1 INTRODUCTION
    2. 12.2 METHODOLOGIES
    3. 12.3 RESULTS
    4. 12.4 CONCLUSION
  18. 13 Advanced Encryption Standard (AES) Implementation in Embedded Systems
    1. 13.1 INTRODUCTION
    2. 13.2 FINITE FIELD
    3. 13.3 THE AES
    4. 13.4 HARDWARE IMPLEMENTATIONS FOR AES
    5. 13.5 HIGH-SPEED AES ENCRYPTOR WITH EFFICIENT MERGING TECHNIQUES
    6. 13.6 CONCLUSION
  19. 14 Reconfigurable Architecture for Cryptography over Binary Finite Fields
    1. 14.1 INTRODUCTION
    2. 14.2 BACKGROUND
    3. 14.3 RECONFIGURABLE PROCESSOR
    4. 14.4 RESULTS
    5. 14.5 CONCLUSIONS
  20. Index