The core component of the scheduler consists of the exception handler associated with the system interrupt events, such as PendSV and SVCall. On Cortex-M, a PendSV exception can be triggered at any time by the software, setting the PENDSET flag, corresponding to bit 28 of the interrupt control and state register, located in the SCB at address 0xE000ED04. A simple macro is defined to initiate the context switch by setting the flag:
#define SCB_ICSR (*((volatile uint32_t *)0xE000ED04))#define schedule() SCB_ICSR |= (1 << 28)
The call to schedule from the kernel, and all the subsequent calls, would cause a context switch, which can now be implemented in the PendSV handler. To complete a context switch, the handler has to perform ...
