You are previewing Embedded SoPC Design with Nios II Processor and Verilog Examples.
O'Reilly logo
Embedded SoPC Design with Nios II Processor and Verilog Examples

Book Description

Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog

An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well—allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop specialized hardware accelerators for computation-intensive tasks.

Utilizing an Altera FPGA prototyping board and its Nios II soft-core processor, Embedded SoPC Design with Nios II Processor and Verilog Examples takes a "learn by doing" approach to illustrate the hardware and software design and development process by including realistic projects that can be implemented and tested on the board.

Emphasizing hardware design and integration throughout, the book is divided into four major parts:

  • Part I covers HDL and synthesis of custom hardware

  • Part II introduces the Nios II processor and provides an overview of embedded software development

  • Part III demonstrates the design and development of hardware and software of several complex I/O peripherals, including a PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card

  • Part IV provides several case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology

While designing and developing an embedded SoPC can be rewarding, the learning can be a long and winding journey. This book shows the trail ahead and guides readers through the initial steps to exploit the full potential of this emerging methodology.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. DEDICATION
  5. CONTENTS
  6. PREFACE
    1. Focus and audience
    2. Logistics
    3. Book organization
    4. Companion Website
  7. ACKNOWLEDGMENTS
  8. CHAPTER 1: OVERVIEW OF EMBEDDED SYSTEM
    1. 1.1 INTRODUCTION
    2. 1.2 SYSTEM DESIGN REQUIREMENTS
    3. 1.3 EMBEDDED SOPC SYSTEMS
    4. 1.4 BOOK ORGANIZATION
    5. 1.5 BIBLIOGRAPHIC NOTES
  9. PART I: BASIC DIGITAL CIRCUITS DEVELOPMENT
    1. CHAPTER 2: GATE-LEVEL COMBINATIONAL CIRCUIT
      1. 2.1 INTRODUCTION
      2. 2.2 GENERAL DESCRIPTION
      3. 2.3 BASIC LEXICAL ELEMENTS AND DATA TYPES
      4. 2.4 DATA TYPES
      5. 2.5 PROGRAM SKELETON
      6. 2.6 STRUCTURAL DESCRIPTION
      7. 2.7 TESTBENCH
      8. 2.8 BIBLIOGRAPHIC NOTES
      9. 2.9 SUGGESTED EXPERIMENTS
    2. CHAPTER 3: OVERVIEW OF FPGA AND EDA SOFTWARE
      1. 3.1 FPGA
      2. 3.2 OVERVIEW OF THE ALTERA DE1 AND DE2 BOARDS
      3. 3.3 DEVELOPMENT FLOW
      4. 3.4 OVERVIEW OF QUARTUS II
      5. 3.5 SHORT TUTORIAL OF QUARTUS II
      6. 3.6 SHORT TUTORIAL ON THE MODELSIM HDL SIMULATOR
      7. 3.7 BIBLIOGRAPHIC NOTES
      8. 3.8 SUGGESTED EXPERIMENTS
    3. CHAPTER 4: RT-LEVEL COMBINATIONAL CIRCUIT
      1. 4.1 OPERATORS
      2. 4.2 ALWAYS BLOCK FOR A COMBINATIONAL CIRCUIT
      3. 4.3 IF STATEMENT
      4. 4.4 CASE STATEMENT
      5. 4.5 ROUTING STRUCTURE OF CONDITIONAL CONTROL CONSTRUCTS
      6. 4.6 GENERAL CODING GUIDELINES FOR AN ALWAYS BLOCK
      7. 4.7 PARAMETER AND CONSTANT
      8. 4.8 DESIGN EXAMPLES
      9. 4.9 BIBLIOGRAPHIC NOTES
      10. 4.10 SUGGESTED EXPERIMENTS
    4. CHAPTER 5: REGULAR SEQUENTIAL CIRCUIT
      1. 5.1 INTRODUCTION
      2. 5.2 HDL CODE OF THE FF AND REGISTER
      3. 5.3 SIMPLE DESIGN EXAMPLES
      4. 5.4 TESTBENCH FOR SEQUENTIAL CIRCUITS
      5. 5.5 TIMING ANALYSIS
      6. 5.6 CASE STUDY
      7. 5.7 CYCLONE II DEVICE EMBEDDED MEMORY MODULE
      8. 5.8 BIBLIOGRAPHIC NOTES
      9. 5.9 SUGGESTED EXPERIMENTS
    5. CHAPTER 6: FSM
      1. 6.1 INTRODUCTION
      2. 6.2 FSM CODE DEVELOPMENT
      3. 6.3 DESIGN EXAMPLES
      4. 6.4 BIBLIOGRAPHIC NOTES
      5. 6.5 SUGGESTED EXPERIMENTS
    6. CHAPTER 7: FSMD
      1. 7.1 INTRODUCTION
      2. 7.2 CODE DEVELOPMENT OF AN FSMD
      3. 7.3 DESIGN EXAMPLES
      4. 7.4 BIBLIOGRAPHIC NOTES
      5. 7.5 SUGGESTED EXPERIMENTS
    7. CHAPTER 8: SELECTED TOPICS OF VERILOG
      1. 8.1 BLOCKING VERSUS NONBLOCKING ASSIGNMENT
      2. 8.2 ALTERNATIVE CODING STYLE FOR SEQUENTIAL CIRCUIT
      3. 8.3 USE OF THE SIGNED DATA TYPE
      4. 8.4 USE OF FUNCTION IN SYNTHESIS
      5. 8.5 ADDITIONAL CONSTRUCTS FOR TESTBENCH DEVELOPMENT
      6. 8.6 BIBLIOGRAPHIC NOTES
      7. 8.7 SUGGESTED EXPERIMENTS
  10. PART II: BASIC NIOS II SOFTWARE DEVELOPMENT
    1. CHAPTER 9: NIOS II PROCESSOR OVERVIEW
      1. 9.1 INTRODUCTION
      2. 9.2 REGISTER FILE AND ALU
      3. 9.3 MEMORY AND I/O ORGANIZATION
      4. 9.4 EXCEPTION AND INTERRUPT HANDLER
      5. 9.5 JTAG DEBUG MODULE
      6. 9.6 BIBLIOGRAPHIC NOTES
      7. 9.7 SUGGESTED PROJECTS
    2. CHAPTER 10: NIOS II SYSTEM DERIVATION AND LOW-LEVEL ACCESS
      1. 10.1 DEVELOPMENT FLOW REVISITED
      2. 10.2 NIOS II HARDWARE GENERATION TUTORIAL
      3. 10.3 NIOS II SBT GUI TUTORIAL
      4. 10.4 SYSTEM ID CORE FOR HARDWARE-SOFTWARE CONSISTENCY
      5. 10.5 DIRECT LOW-LEVEL I/O ACCESS
      6. 10.6 ROBUST LOW-LEVEL I/O ACCESS
      7. 10.7 SOME C TECHNIQUES FOR LOW-LEVEL I/O OPERATIONS
      8. 10.8 SOFTWARE DEVELOPMENT
      9. 10.9 BIBLIOGRAPHIC NOTES
      10. 10.10 SUGGESTED EXPERIMENTS
      11. 10.11 COMPLETE PROGRAM LISTING
    3. CHAPTER 11: PREDESIGNED NIOS II I/O PERIPHERALS
      1. 11.1 OVERVIEWS
      2. 11.2 PIO CORE
      3. 11.3 JTAG UART CORE
      4. 11.4 INTERNAL TIMER CORE
      5. 11.5 ENHANCED FLASHING-LED NIOS II SYSTEM
      6. 11.6 SOFTWARE DEVELOPMENT OF ENHANCED FLASHING-LED SYSTEM
      7. 11.7 DEVICE DRIVER ROUTINES
      8. 11.8 TASK ROUTINES
      9. 11.9 SOFTWARE CONSTRUCTION AND TESTING
      10. 11.10 BIBLIOGRAPHIC NOTES
      11. 11.11 SUGGESTED EXPERIMENTS
      12. 11.12 COMPLETE PROGRAM LISTING
    4. CHAPTER 12: PREDESIGNED NIOS II I/O DRIVERS AND HAL API
      1. 12.1 OVERVIEW OF HAL
      2. 12.2 BSP
      3. 12.3 HAL-BASED FLASHING-LED PROGRAM
      4. 12.4 DEVICE DRIVER CONSIDERATION
      5. 12.5 BIBLIOGRAPHIC NOTES
      6. 12.6 SUGGESTED EXPERIMENTS
      7. 12.7 COMPLETE PROGRAM LISTING
    5. CHAPTER 13: INTERRUPT AND ISR
      1. 13.1 INTERRUPT PROCESSING IN THE HAL FRAMEWORK
      2. 13.2 INTERRUPT-BASED FLASHING-LED PROGRAM
      3. 13.3 INTERRUPT AND SCHEDULING
      4. 13.4 BIBLIOGRAPHIC NOTES
      5. 13.5 SUGGESTED EXPERIMENTS
      6. 13.6 COMPLETE PROGRAM LISTING
  11. PART III: CUSTOM I/O PERIPHERAL DEVELOPMENT
    1. CHAPTER 14: CUSTOM I/O PERIPHERAL WITH PIO CORES
      1. 14.1 INTRODUCTION
      2. 14.2 INTEGRATION OF DIVISION CIRCUIT TO A NIOS II SYSTEM
      3. 14.3 TESTING
      4. 14.4 SUGGESTED EXPERIMENTS
    2. CHAPTER 15: AVALON INTERCONNECT AND SOPC COMPONENT
      1. 15.1 INTRODUCTION
      2. 15.2 AVALON MM INTERFACE
      3. 15.3 SYSTEM INTERCONNECT FABRIC FOR AVALON INTERFACE
      4. 15.4 SOPC I/O COMPONENT WRAPPING CIRCUIT
      5. 15.5 SOPC COMPONENT CONSTRUCTION TUTORIAL
      6. 15.6 TESTING
      7. 15.7 BIBLIOGRAPHIC NOTES
      8. 15.8 SUGGESTED EXPERIMENTS
    3. CHAPTER 16: SRAM AND SDRAM CONTROLLERS
      1. 16.1 MEMORY RESOURCES OF DE1 BOARD
      2. 16.2 BRIEF OVERVIEW OF TIMING AND CLOCK MANAGEMENT
      3. 16.3 OVERVIEW OF SRAM
      4. 16.4 SRAM CONTROLLER IP CORE
      5. 16.5 OVERVIEW OF DRAM
      6. 16.6 OVERVIEW OF SDRAM
      7. 16.7 SDRAM CONTROLLER AND PLL
      8. 16.8 TESTING SYSTEM
      9. 16.9 BIBLIOGRAPHIC NOTES
      10. 16.10 SUGGESTED EXPERIMENTS
      11. 16.11 COMPLETE PROGRAM LISTING
    4. CHAPTER 17: PS2 KEYBOARD AND MOUSE
      1. 17.1 INTRODUCTION
      2. 17.2 PS2 RECEIVING SUBSYSTEM
      3. 17.3 PS2 TRANSMITTING SUBSYSTEM
      4. 17.4 COMPLETE PS2 SYSTEM
      5. 17.5 PS2 CONTROLLER IP CORE DEVELOPMENT
      6. 17.6 PS2 DRIVER
      7. 17.7 KEYBOARD DRIVER
      8. 17.8 MOUSE DRIVER
      9. 17.9 TEST
      10. 17.10 USE OF BOOK'S CUSTOM IP CORES
      11. 17.11 BIBLIOGRAPHIC NOTES
      12. 17.12 SUGGESTED EXPERIMENTS
      13. 17.13 COMPLETE PROGRAM LISTING
    5. CHAPTER 18: VGA CONTROLLER
      1. 18.1 INTRODUCTION
      2. 18.2 VGA SYNCHRONIZATION
      3. 18.3 SRAM-BASED VIDEO RAM CONTROLLER
      4. 18.4 PALETTE CIRCUIT
      5. 18.5 VIDEO CONTROLLER IP CORE DEVELOPMENT
      6. 18.6 VIDEO DRIVER
      7. 18.7 MOUSE PROCESSING ROUTINES
      8. 18.8 TESTING PROGRAM
      9. 18.9 BITMAP FILE PROCESSING
      10. 18.10 BIBLIOGRAPHIC NOTES
      11. 18.11 SUGGESTED EXPERIMENTS
      12. 18.12 SUGGESTED PROJECTS
      13. 18.13 COMPLETE PROGRAM LISTING
    6. CHAPTER 19: AUDIO CODEC CONTROLLER
      1. 19.1 INTRODUCTION
      2. 19.2 I 2 C CONTROLLER
      3. 19.3 CODEC DATA ACCESS CONTROLLER
      4. 19.4 AUDIO CODEC CONTROLLER IP CORE DEVELOPMENT
      5. 19.5 CODEC DRIVER
      6. 19.6 TESTING PROGRAM
      7. 19.7 AUDIO FILE PROCESSING
      8. 19.8 BIBLIOGRAPHIC NOTES
      9. 19.9 SUGGESTED EXPERIMENTS
      10. 19.10 SUGGESTED PROJECTS
      11. 19.11 COMPLETE PROGRAM LISTING
    7. CHAPTER 20: SD CARD CONTROLLER
      1. 20.1 OVERVIEW OF SD CARD
      2. 20.2 SPI CONTROLLER
      3. 20.3 SPI CONTROLLER IP CORE DEVELOPMENT
      4. 20.4 SD CARD PROTOCOL
      5. 20.5 SPI AND SD CARD DRIVER
      6. 20.6 FILE ACCESS
      7. 20.7 TESTING PROGRAM
      8. 20.8 PERFORMANCE OF SD CARD DATA TRANSFER
      9. 20.9 BIBLIOGRAPHIC NOTES
      10. 20.10 SUGGESTED EXPERIMENTS
      11. 20.11 SUGGESTED PROJECTS
      12. 20.12 COMPLETE PROGRAM LISTING
  12. PART IV: HARDWARE ACCELERATOR CASE STUDIES
    1. CHAPTER 21: GCD ACCELERATOR
      1. 21.1 INTRODUCTION
      2. 21.2 SOFTWARE IMPLEMENTATION
      3. 21.3 HARDWARE IMPLEMENTATION
      4. 21.4 TIME MEASUREMENT
      5. 21.5 GCD ACCELERATOR IP CORE DEVELOPMENT
      6. 21.6 TESTING PROGRAM
      7. 21.7 PERFORMANCE COMPARISON
      8. 21.8 BIBLIOGRAPHIC NOTES
      9. 21.9 SUGGESTED EXPERIMENTS
      10. 21.10 COMPLETE PROGRAM LISTING
    2. CHAPTER 22: MANDELBROT SET FRACTAL ACCELERATOR
      1. 22.1 INTRODUCTION
      2. 22.2 FIXED-POINT ARITHMETIC
      3. 22.3 SOFTWARE IMPLEMENTATION OF CALC_FRAC_POINT()
      4. 22.4 HARDWARE IMPLEMENTATION OF CALC_FRAC_POINT()
      5. 22.5 MANDELBROT SET FRACTAL ACCELERATOR IP CORE DEVELOPMENT
      6. 22.6 TESTING PROGRAM
      7. 22.7 DISCUSSION
      8. 22.8 BIBLIOGRAPHIC NOTES
      9. 22.9 SUGGESTED EXPERIMENTS
      10. 22.10 SUGGESTED PROJECTS
      11. 22.11 COMPLETE PROGRAM LISTING
    3. CHAPTER 23: DIRECT DIGITAL FREQUENCY SYNTHESIS
      1. 23.1 INTRODUCTION
      2. 23.2 DESIGN AND IMPLEMENTATION
      3. 23.3 DDFS IP CORE DEVELOPMENT
      4. 23.4 DDFS DRIVER
      5. 23.5 TESTING
      6. 23.6 BIBLIOGRAPHIC NOTES
      7. 23.7 SUGGESTED EXPERIMENTS
      8. 23.8 SUGGESTED PROJECTS
      9. 23.9 COMPLETE PROGRAM LISTING
  13. REFERENCES
  14. INDEX