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Embedded Signal Processing with the Micro Signal Architecture by Sen M. Kuo, Woon-Seng Gan

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Chapter 7

Memory System and Data Transfer

We introduced several techniques to process digital signals in sample and block processing modes in Chapter 6. This chapter describes how to transfer data between the ADC and memory, within memory spaces, and between memory and peripherals with DMA. We present the unique caching mechanism of the Blackfin processor to speed up the transfer of program and data from external memory to internal memory.

7.1    OVERVIEW OF SIGNAL ACQUISITION AND TRANSFER TO MEMORY

This section presents the operations of the CODEC and its interface with the Blackfin processor. We use a simple talk-through program to illustrate a typical real-time signal processing chain from converting analog signal to digital samples to processing the data, and reconstructing the processed digital signal back to the analog form.

7.1.1    Understanding the CODEC

A CODEC consists of both ADC and DAC with associated analog antialiasing and reconstruction low-pass filters. For example, the Analog Devices AD1836A [41] shown in Figure 7.1 is a single-chip CODEC that provides two stereo ADCs and three stereo DACs. These ADCs and DACs can operate in 16-, 18-, 20-, or 24-bit resolution. An N-bit ADC produces 2N digital output numbers, and an N-bit DAC has 2N analog output levels. To achieve a fine resolution to encode a small signal, the value of N must be carefully chosen. For example, a 5-V peak-to-peak (or full scale) signal can be applied to a 16-bit CODEC to obtain a voltage resolution ...

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