R1.4 Physical Design Automation
[Chang 2004] Y.-W. Chang, S.-P. Lin, MR: A new framework for multilevel full-chip routing IEEE Trans, on Computer-Aided Design 23 5 May 2004, 793-800
[Chang 2007] Y.-W. Chang, T.-C. Chen, H.-Y. Chen, Physical design for system-on-a-chip Y.-L. Lin, Essential Issues in SOC Design 2007 Springer Boston
[Chen 2006] T.-C. Chen, Y.-W. Chang, Modern floorplanning based on B*-trees and fast simulated annealing IEEE Trans, on Computer-Aided Design 25 4 April 2006, 637-650
[Chen 2008] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, Y.-W. Chang, NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints IEEE Trans, on Computer-Aided Design 27 7 July 2008, 1228-1240 ...
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