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Electronic Design Automation

Book Description

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.

  • Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
  • Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
  • Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
  • Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes

Table of Contents

  1. Brief Table of Contents
  2. Table of Contents
  3. The Morgan Kaufmann Series in Systems on Silicon
  4. Copyright
  5. Preface
  6. In the Classroom
  7. Acknowledgments
  8. Contributors
  9. About the Editors
  10. Chapter 1. Introduction
  11. Bibliography
  12. References
  13. R1.0 Books
  14. R1.1 Overview of Electronic Design Automation
  15. R1.2 Logic Design Automation
  16. R1.3 Test Automation
  17. R1.4 Physical Design Automation
  18. R1.5 Concluding Remarks
  19. Chapter 2. Fundamentals of CMOS design
  20. Bibliography
  21. References
  22. R2.0 Books
  23. R2.6 Low-Power Design
  24. Chapter 3. Design for testability
  25. Bibliography
  26. References
  27. R3.0 Books
  28. R3.1 Introduction
  29. R3.2 Testability Analysis
  30. R3.3 Scan Design
  31. R3.4 Logic Built-in Self-Test
  32. R3.5 Test Compression
  33. R3.6 Concluding Remarks
  34. Chapter 4. Fundamentals of algorithms
  35. Bibliography
  36. References
  37. R4.1 Books
  38. R4.2 Computational Complexity
  39. R4.3 Graph Algorithms
  40. R4.4 Heuristic Algorithms
  41. R4.5 Mathematical Programming
  42. Chapter 5. Electronic system-level design and high-level synthesis
  43. Bibliography
  44. References
  45. R5.0 Books
  46. R5.1 Introduction
  47. R5.7 Concluding Remarks
  48. Chapter 6. Logic synthesis in a nutshell
  49. Bibliography
  50. References
  51. R6.0 Books
  52. R6.1 Introduction
  53. R6.2 Data Structures for Boolean Representation and Reasoning
  54. R6.3 Combinational Logic Minimization
  55. R6.4 Technology Mapping
  56. R6.5 Timing Analysis
  57. R6.6 Timing Optimization
  58. R6.7 Trends in Logic Synthesis
  59. Chapter 7. Test synthesis
  60. Bibliography
  61. References
  62. R7.0 Books
  63. R7.1 Introduction
  64. R7.2 Scan Design
  65. R7.3 Logic Built-in Self-Test (BIST) Design
  66. R7.4 RTL Design for Testability
  67. R7.5 Concluding Remarks
  68. Chapter 8. Logic and circuit simulation
  69. Bibliography
  70. References
  71. R8.0 Books
  72. R8.1 Introduction
  73. R8.2 Logic Simulation Models
  74. R8.3 Logic Simulation Techniques
  75. R8.4 Hardware-Accelerated Logic Simulation
  76. R8.5 Circuit Simulation Models
  77. R8.7 Simulation of VLSI Interconnects
  78. R8.8 Simulation of Nonlinear Devices
  79. R8.9 Concluding Remarks
  80. Chapter 9. Functional verification
  81. Bibliography
  82. References
  83. R9.0 Books
  84. R9.1 Introduction
  85. R9.2 Verification Hierarchy
  86. R9.3 Measuring Verification Quality
  87. R9.4 Simulation-Based Approach
  88. R9.5 Formal Approaches
  89. R9.6 Advanced Research
  90. Chapter 10. Floorplanning
  91. Bibliography
  92. References
  93. R10.0 Books
  94. R10.1 Introduction
  95. R10.2 Simulated Annealing Approach
  96. R10.3 Analytical Approach
  97. R10.4 Modern Floorplanning Considerations
  98. R10.5 Concluding Remarks
  99. Chapter 11. Placement
  100. Bibliography
  101. References
  102. R11.0 Books
  103. R11.1 Introduction
  104. R11.2 Problem Formulations
  105. R11.3 Global Placement: Partitioning-Based Approach
  106. R11.4 Global Placement: Simulated Annealing Approach
  107. R11.5 Global Placement: Analytical Approach
  108. R11.6 Legalization
  109. R11.7 Detailed Placement
  110. R11.8 Concluding Remarks
  111. Chapter 12. Global and detailed routing
  112. Bibliography
  113. References
  114. R12.0 Books
  115. R12.2 Problem Definition
  116. R12.3 General-Purpose Routing
  117. R12.4 Global Routing
  118. R12.5 Detailed Routing
  119. R12.6 Modern Routing Considerations
  120. R12.8 Exercises
  121. Chapter 13. Synthesis of clock and power/ground networks
  122. Bibliography
  123. References
  124. R13.0 Books
  125. R13.2 Design Considerations
  126. R13.3 Clock Network Design
  127. R13.4 Power/Ground Network Design
  128. Chapter 14. Fault simulation and test generation
  129. Bibliography
  130. References
  131. R14.0 Books
  132. R14.1 Fault Collapsing
  133. R14.2 Fault Simulation
  134. R14.3 Test Generation
  135. R14.4 Advanced Test Generation
  136. R14.5 Concluding Remarks