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Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication

Book Description

Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication is the one of the first compilations written to demonstrate this future for network -on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, this book represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

Table of Contents

  1. Copyright
  2. Editorial Advisory Board
  3. Foreword
  4. Preface
    1. SECTION 1: INTRODUCTION TO RECONFIGURABLE NETWORK-ON-CHIP
    2. SECTION 2: DESIGN METHODS FOR RECONFIGURABLE NOC DESIGN
    3. SECTION 3: HIGH-LEVEL PROGRAMMING OF RECONFIGURABLE NOC-BASED SOCS
    4. SECTION 4: SIMULATION FRAMEWORK FOR FAST RECONFIGURABLE NOC EMULATION
    5. SECTION 5: STATE-OF-THE-ART RECONFIGURABLE NOC DESIGNS
  5. Acknowledgment
  6. 1. Introduction to Reconfigurable Network-on-Chip
    1. 1. A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems
      1. ABSTRACT
      2. INTRODUCTION
      3. RELATED WORK IN DRS
      4. DSRS CONCEPTUAL ARCHITECTURE
        1. Configuration Controllers
        2. Reconfigurable Interface
        3. Communication Infrastructure
        4. Configuration Ports
      5. PROPOSED DSRS INFRASTRUCTURE
        1. Repositories
        2. Reconfigurable Interface
        3. Configuration Ports
        4. Configuration Controller
        5. DSRS Infrastructure
      6. ARTEMIS NoC
        1. Hermes NoC
        2. Artemis NoC
          1. Control Packets
          2. Reconfigurable IP to Router Interface
      7. DESIGN FLOWS FOR DRS
        1. Reconfigurable Interfaces Insertion
        2. Placement Constraints
        3. Routing Verification / Modification
        4. Partial Configurations Generation
        5. Core Relocation
      8. CASE STUDIES
        1. OPB-Based DSRS Description
        2. ARTEMIS-Based DSRS Description
        3. Infrastructure Comparison
      9. CONCLUSION AND FUTURE WORK
      10. REFERENCES
        1. KEY TERMS AND DEFINITIONS
      11. ENDNOTE
    2. 2. Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. STATIC NOC DESIGN
        1. Customization of a NoC
      5. ROUTER DESIGN
        1. Customization Methods for a Router
        2. Analysis of the Customization Methods
          1. Routing Algorithm
          2. Number and Size of Ports
          3. Size of Buffers
          4. Switch Matrix
        3. Tradeoffs With the Customization Methods
      6. RUNTIME ADAPTIVE ROUTER
        1. Routing Algorithm
        2. Switching Algorithm
        3. Number and Size of Ports
        4. Size of Buffers
        5. Switch Matrix
        6. Concluding Remarks
      7. FUTURE RESEARCH DIRECTIONS
      8. CONCLUSION
      9. REFERENCES
      10. ENDNOTE
    3. 3. Keys for Administration of Reconfigurable NoC: Self-Adaptive Network Interface Case Study
      1. ABSTRACT
      2. INTRODUCTION
      3. MODELING OF RECONFIGURABLE NETWORK-ON-CHIP (RNOC)
        1. Dynamic Reconfiguration Model
        2. RNoC Model Dimensions
          1. Administration
          2. Infrastructure
          3. Protocols
        3. State of the Art Synthesis
      4. RECONFIGURABLE NETWORK-ON-CHIP ADMINISTRATION STRATEGY
        1. Global / Local Strategy
        2. Evolution of NoC Design Methodology
        3. Local Management: Self-Adaptive Network Interface (SANI)
          1. SANI Description
          2. SANI Reconfiguration Mechanism
          3. Hardware Test-Bench Conditions
          4. Results
      5. CONCLUSION
      6. REFERENCES
      7. KEY TERMS AND DEFINITIONS
    4. 4. An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. PRELIMINARIES
        1. Dynamic Partial Reconfiguration
        2. Overview of Network-on-Chip
        3. Hybrid Architecture for RNoC
        4. Basic Assumptions
      5. COMMUNICATION ARCHITECTURES FOR RNOC
        1. Single Output FIFO-Based Architecture
        2. Multiple Output FIFO-Based Architecture
        3. Shared Memory-Based Architecture
      6. ARCHITECTURE EVALUATION AND EXPERIMENTS
        1. Evaluation of Communication Memory Overhead
        2. Performance Analysis
          1. JPEG Application
          2. Encryption and Decryption Applications
          3. Analysis
      7. CONCLUSION
      8. REFERENCES
  7. 2. Design Methods for Reconfigurable NoC Design
    1. 5. Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
        1. FPGAs Reconfiguration
        2. Target Architecture
        3. 1D and 2D Placement and Reconfiguration Constraints
        4. Relocation Technique
        5. Homogeneity
        6. 2D Reconfigurable Homogeneous and Non-Homogeneous Architectures
          1. 2D Reconfigurable Homogeneous Approach
          2. 2D Reconfigurable Non-Homogeneous Approach
        7. Comparison between the Homogeneous and the Non Homogeneous Approach
          1. Area Usage of the System
          2. Available Memory
          3. Level of Re-Use and Adaptability
          4. Internal Structure of the System
      4. DESIGN METHODOLOGIES
        1. Network-on-Chip Reconfiguration
        2. Computational Cores Reconfiguration
          1. Mapping Problem
          2. Related Works
          3. High-Level Specification of Communication Constraints
          4. Mapping Algorithms
            1. Exhaustive Algorithms
            2. Heuristic Algorithms
            3. NSGA2
            4. Custom Genetic Algorithms
        3. Network-on-Chip and Computational Cores Reconfiguration
        4. Experimental Results
      5. CONCLUSION
      6. REFERENCES
        1. KEY TERMS AND DEFINITIONS
      7. ENDNOTES
    2. 6. From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology
      1. ABSTRACT
      2. INTRODUCTION
      3. NETWORK ON CHIPS
        1. OSI to NoC Model
        2. Concepts Related to Network on Chip
          1. Topology
          2. Routing Algorithms
          3. Problems on Routing
          4. Switching Techniques
          5. Network Flow Control
        3. NoC Design Challenges
      4. MODEL DRIVEN ENGINEERING
      5. GASPARD: MARTE COMPLIANT CO-DESIGN FRAMEWORK
      6. DEPLOYMENT LEVEL: A DETAILED OVERVIEW
      7. PROPOSED DESIGN FLOW
      8. CASE STUDY
        1. Modeling of a Hypercube Topology
        2. Modeling of a Mesh Topology
        3. Modeling of a Star Topology
      9. CONCLUSION
      10. REFERENCES
    3. 7. Dynamic Reconfigurable NoCs: Characteristics and Performance Issues
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
        1. Target Reconfigurable Architecture
        2. Bus-Macros
        3. Packet-Switching Routing
        4. Factors, Requirements and Constraints of Reconfigurable NoCs Design
          1. Latency
          2. Bandwidth
          3. Throughput
          4. Resource Allocation
          5. Scalability
          6. Reusability
      4. STATE OF THE ART
        1. XPipes
        2. DyNoC
        3. CuNoC
        4. CoNoChi
      5. ISSUES IN DYNAMIC RECONFIGURABLE NOCS DESIGN
        1. A Layered Approach
          1. Layers Definition
        2. A Packet-Switched Communication Infrastructure
        3. Routing Mechanisms
          1. Problem Description
          2. Target-Based vs. Initiator-Based Routing
          3. A Hybrid Approach
        4. A Topology Adaptive Network
        5. Communication Protocol Support
          1. Information Units Structure
          2. Header Packet
          3. Data Packet
          4. End Communication Flow
          5. Reply Packet
          6. Route Update and Dynamic Slave Insertion
      6. RECONFIGURABLE NOCS IMPLEMENTATION DETAILS
        1. Bus-Macro Placement
          1. Reconfigurable Regions Sizing
          2. Physical Bus-Macros Placement
          3. Communication Channel Width
        2. Switch Design
          1. Input Stage Implementation Details
          2. Output Stage Implementation Details
        3. Routing Mechanism
          1. Routing Tables
      7. CONCLUSION
      8. REFERENCES
        1. KEY TERMS AND DEFINITIONS
      9. ENDNOTE
  8. 3. High-Level Programming of Reconfigurable NoC-based SoCs
    1. 8. High-Level Programming of Dynamically Reconfigurable NoC-Based Heterogeneous Multicore SoCs
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. REQUIREMENTS ON SOC INFRASTRUCTURES FOR DYNAMIC RECONFIGURATION
        1. Characteristics of NoC-Based Coarse-Grained Reconfigurable Architectures (CGRAs)
        2. Requirements on Dynamic Reconfiguration Infrastructures
      5. THE GANNET DYNAMIC RECONFIGURATION INFRASTRUCTURE
        1. The Ip-Core-as-Service Abstraction
        2. System Overview
        3. Operation of the Gannet Service Manager
      6. THE GANNET LANGUAGE
        1. Language Syntax
        2. Language Semantics
        3. Custom Control Constructs
          1. Lexical Scoping
          2. Conditional Branching
          3. Function Definition and Application
          4. List Operations
        4. Streaming data processing
        5. Compilation of Gannet Code into packets
        6. Compiling High-Level Languages into Gannet
      7. THE GANNET MACHINE MODEL
        1. Notation and Definitions
          1. Notation
          2. Definitions
          3. Small-Step Semantics
        2. Packet Processing by the Services
          1. Packet Transfer between Services
          2. Marshalling Action Set M
          3. Processing Action Set P
          4. Hardware Memory Management
        3. Control and Computational Service Semantics
          1. Computational Service Semantics
          2. Control Service Semantics
            1. Lexically Scoped Variables
            2. Lambda Functions
        4. Multi-Operation Services
        5. Dynamic Service Configuration
        6. Separation of Control Flow from Data Flow
          1. Bottleneck in Central-Memory SoC Architectures
          2. Redirection of Data Flows
        7. Pipelined Streaming Data Processing
      8. EXAMPLES OF DYNAMIC RECONFIGURATION
        1. Example of Dynamic Data path Reconfiguration
        2. Example of Dynamic Service Reconfiguration
      9. IMPLEMENTATION OF THE DYNAMIC RECONFIGURATION INFRASTRUCTURE
        1. Assembler and Compiler
        2. Behavioural Model
        3. FPGA Implementation
        4. Performance Evaluation
          1. Choice of Application Domain
          2. Choice of Network on Chip
          3. Design of Experiment
          4. Results
      10. CONCLUSION AND FUTURE WORK
      11. REFERENCES
        1. KEY TERMS AND DEFINITIONS
      12. ENDNOTES
  9. 4. Simulation Framework for Fast Reconfigurable NoC Emulation
    1. 9. Dynamic Reconfigurable NoC (DRNoC) Architecture: Application to Fast NoC Emulation
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
        1. NoCs for Reconfigurable Systems
        2. Nocs for Runtime Reconfigurable Systems
        3. On-Chip Communications Adaptability in Reconfigurable Systems
      4. DYNAMIC RECONFIGURABLE NOC (DRNOC) ARCHITECTURE
        1. DRNoC Architecture
        2. DRNoC Addressing
        3. DRNoc Noc Communication Scheme Packet Format
        4. DRNoC Reconfigurability
        5. DRNoC Mapping to FPGAS
        6. DRNoC Routers
        7. DRNoC Design Resources
        8. DRNoCs Design Resource Area Requirements
        9. DRNoC NoC Model Generation Tool: DRNoCGEN
        10. Reconfigurability & Current Technology Restrictions
        11. NoCs for Runtime Reconfigurable Systems Feature Summary
        12. DRNoC Emulation Framework: Fast Emulation Based on Partial Reconfiguration.
          1. Emulation Working Flow
          2. DRNoC Emulation Framework
          3. DRNoC Emulation SW
        13. DRNoC Validation Through Use Cases
          1. Evaluation of the DRNoC Emulation System
      5. FUTURE RESEARCH DIRECTIONS
      6. CONCLUSION
      7. REFERENCES
      8. ADDITIONAL READING
  10. 5. State-of-the-Art Reconfigurable NoC Designs
    1. 10. Dynamically Reconfigurable NoC for Future Heterogeneous Multi-Core Architectures
      1. ABSTRACT
      2. INTRODUCTION
      3. HISTORY OF DRNOC
      4. PROPOSED DYNAMICALLY RECONFIGURABLE NOC
      5. NETWORK ARCHITECTURE AND CONTROL
        1. Transport Layer
        2. Network Layer
          1. Routing Algorithm for Packet Switching
        3. Data Link Layer
        4. Physical Layer
      6. SYSTEMC MODELING OF DRNOC
        1. Modeling Level
        2. Router Modeling
        3. Hardware Reconfigurability
        4. Network Analysis
        5. Explanation of Simulations
      7. SUMMARY
      8. REFERENCES
    2. 11. Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks
      1. ABSTRACT
      2. INTRODUCTION
      3. NETWORK ARCHITECTURE
        1. Base Router Architecture
        2. Support for Error Correction
      4. IMPLEMENTATION OF DVFS ON NOCS
      5. RELIABILITY CONSIDERATIONS UNDER DYNAMIC VARIATIONS OF VOLTAGE
        1. Error Rate Variation
        2. Error Correction Power
      6. EXPERIMENTAL SETUP
        1. Reconfigurable ECC Support
      7. EXPERIMENTAL RESULTS
        1. Performance Benefits
        2. Power Benefits
        3. Experiments with Threshold Levels
        4. Varying Network Size
        5. Varying Traffic Patterns
        6. Varying Injection Rate
      8. APPLICATION RESULTS
      9. RELATED WORK
      10. CONCLUSION
      11. ACKNOWLEDGMENT
      12. REFERENCES
      13. KEY TERMS AND DEFINITIONS
    3. 12. SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs
      1. ABSTRACT
      2. INTRODUCTION
      3. RADIATION ENVIRONMENT
      4. VIRTEX-4 ARCHITECTURE
      5. RADIATION EFFECTS IN VIRTEX FPGAS
      6. DYNAMIC PARTIAL RECONFIGURATION
      7. DYNAMIC RECONFIGURABLE SOC BASED ON BUS STRUCTURE
      8. NETWORK-ON-CHIP APPROACH FOR DYNAMIC RECONFIGURABLE SOC
      9. SPACECRAFT COMMUNICATION ARCHITECTURES
      10. SPACEWIRE
        1. Character Level
        2. Exchange Level
        3. Packet Level
        4. Network Level
        5. SpaceWire Error Recovery Schemes
      11. SOCWIRE CODEC
      12. SOCWIRE SWITCH
      13. DYNAMIC RECONFIGURABLE SOC
      14. FUTURE RESEARCH
      15. CONCLUSION
      16. REFERENCES
      17. KEY TERMS AND DEFINITIONS
    4. 13. A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
        1. NoC Topology
      4. THE RECONFIGURABLE NOC ARCHITECTURE
      5. The NoC Architecture
        1. The Cost of the Proposed NoC Architecture
        2. Flow-Control Mechanism
        3. Energy and Performance-Aware Mapping Algorithm
        4. Core to Network Mapping
        5. Topology and Route Generation
        6. Power and Performance Evaluation
      6. FUTURE RESEARCH DIRECTIONS
      7. CONCLUSION
      8. REFERENCES
      9. ADDITIONAL READING
  11. Compilation of References
  12. About the Contributors