DSL Advances

6.8. Timing Configurations

There are three mode timing operation defined in G.991.2, namely

• Plesiochronous mode

• Plesiochronous with network timing reference

• Bit synchronous mode

Each of these timing modes is described below.

Figure 6.20 shows the transceiver-timing configuration for the plesiochronous timing mode. This is the timing configuration used for classic HDSL operation. The transceiver line clock, that is, the transmit symbol clock, operates independent (free running) from the payload data clock. For this application, the payload timing reference needs to be transferred end to end. In this timing mode, the pulse stuffing operations are enabled, and the payload data clocks (i.e., Tx_Clock signals) are passed end to end. Note that due to ...