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Digital Waveform Generation by Pete Symons

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8 Hardware implementation architectures

In this chapter we investigate hardware implementation of the DDS, sinusoidal and arbitrary waveform generation techniques presented in earlier chapters. We do not concern ourselves with specific target technologies such as FPGAs, but restrict our signal flow descriptions to the ‘register transfer level’ (RTL). The exact implementation technology (e.g. FPGA, ASIC or even hardwired logic) and the partitioning between hardware and embedded software are left to the suitably skilled reader and his or her application-specific requirements. For the most part, implementation of these algorithms, particularly in wide bandwidth applications, is best handled in high speed FPGA or ASIC logic. It is intended that this ...

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