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Digital System Design with SystemVerilog by Mark Zwolinski

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8. Writing Testbenches

Writing a synthesizable model of a piece of hardware is only half (or perhaps less than half) of the design problem. It is essential to know that the model does the task for which it is intended. It would, of course, be possible to do this the hard way—by synthesizing the hardware and testing the design in the final context in which it is to be used. This could be a very expensive and dangerous approach.

The alternative is to verify the hardware before synthesis. In practice, this means that the hardware has to be simulated. In order to simulate a SystemVerilog model, stimuli have to be applied to the model and the responses of the model have to be analyzed. For portability and to avoid having to learn a new set of language ...

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