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Digital System Design with SystemVerilog by Mark Zwolinski

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7. Complex Sequential Systems

In the previous three chapters we looked at combinational and sequential building blocks and the design of state machines. The purpose of this chapter is to see how these various parts can be combined to build complex digital systems.

7.1 Linked State Machines

In principle, any synchronous sequential system could be described by an ASM chart. In practice, this does not make sense. The states of a system, such as a microprocessor, include all the possible values of all the data that might be stored in the system. Therefore, it is usual to partition a design in some way. In this chapter, we show first how an ASM chart, and hence the SystemVerilog model of the state machine, can be partitioned, and second how a conceptual ...

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