Combinational logic is stateless: Changes in inputs are immediately reflected by changes in outputs. In this chapter, we introduce the basic ideas of modeling in SystemVerilog by looking at combinational logic described in terms of gates.
The basic unit of a SystemVerilog design is the
module. For example, a two-input AND gate might be described by:
module And2 (output wire z, input wire x, y);
assign z = x & y;
The words shown in bold are keywords. The module description starts with the keyword
module, followed by the name of the module and a list of inputs and outputs in parentheses. The module finishes with the keyword
endmodule. Note that a semicolon ...