Digital System Clocking: High-Performance and Low-Power Aspects

CHAPTER 4

PIPELINING AND TIMING ANALYSIS

4.1. ANALYSIS OF A SYSTEM THAT USES A FLIP-FLOP

In order to properly analyze the timing parameters associated with the clocked storage elements, we need to analyze the timing situation in a pipelined system. We should start first with the simplest case of a flip-flop and the single clock used in the design. This situation is illustrated in Fig. 4.1. Much of the discussion presented here was taken from the paper by Unger and Tan (1986), with some minor changes in notation.

There are two events that we need to prevent:

1. The data arrive too late to be captured reliably in the next cycle. There are two possible scenarios here: either the data arrived far too late and are completely missed in the next cycle, or they are just sufficiently late to be violating the setup time requirement of the storage element, thus not assuring reliable capture.
2. The data arrive too early (during the same cycle), thus violating the hold time requirement for the flip-flip.

4.1.1. Late Data Arrival Analysis

We cannot assure that the data will be properly captured in either of the cases discussed in the last section, and therefore we are not able to guarantee reliable operation of the system. In order to perform a simple analysis of this system, let us assume that the clock skew and jitter together can cause the maximum deviation of the clock's leading edge for T_L amount of time from the nominal time of arrival (and T_T for the trailing edge). If we set the time reference ...