Digital System Clocking: High-Performance and Low-Power Aspects

Table of contents

1. Cover Page
2. Title Page
3. Copyright
4. Dedication
5. Contents
6. PREFACE
7. CHAPTER 1: INTRODUCTION
   1. 1.1. CLOCKING IN SYNCHRONOUS SYSTEMS
   2. 1.2. SYSTEM CLOCK DESIGN
   3. 1.3. TIMING PARAMETERS
   4. 1.4. CLOCK SIGNAL DISTRIBUTION
8. CHAPTER 2: THEORY OF CLOCKED STORAGE ELEMENTS
   1. 2.1. LATCH-BASED CLOCKED STORAGE ELEMENTS
   2. 2.2. FLIP-FLOP
9. CHAPTER 3: TIMING AND ENERGY PARAMETERS
   1. 3.1. TIMING PARAMETERS
   2. 3.2. ENERGY PARAMETERS
   3. 3.3. INTERFACE WITH CLOCK NETWORK AND COMBINATIONAL LOGIC
10. CHAPTER 4: PIPELINING AND TIMING ANALYSIS
    1. 4.1. ANALYSIS OF A SYSTEM THAT USES A FLIP-FLOP
    2. 4.2. ANALYSIS OF A SYSTEM THAT USES A SINGLE LATCH
    3. 4.3. ANALYSIS OF A SYSTEM WITH A TWO-PHASE CLOCK AND TWO LATCHES IN AN M-S ARRANGEMENT
    4. 4.4. ANALYSIS OF A SYSTEM WITH A SINGLE-PHASE CLOCK AND DUAL-EDGE-TRIGGERED STORAGE ELEMENTS
11. CHAPTER 5: HIGH-PERFORMANCE SYSTEM ISSUES
    1. 5.1. ABSORBING CLOCK UNCERTAINTIES
    2. 5.2. TIME BORROWING
    3. 5.3. TIME BORROWING AND CLOCK UNCERTAINTY
12. CHAPTER 6: LOW-ENERGY SYSTEM ISSUES
    1. 6.1. LOW-SWING CIRCUIT TECHNIQUES
    2. 6.2. CLOCK GATING
    3. 6.3. DUAL-EDGE TRIGGERING
    4. 6.4. GLITCH ROBUST DESIGN
13. CHAPTER 7: SIMULATION TECHNIQUES
    1. 7.1. THE METHOD OF LOGICAL EFFORT
    2. 7.2. ENVIRONMENT SETUP
    3. 7.3. APPENDIX
14. CHAPTER 8: STATE-OF-THE-ART CLOCKED STORAGE ELEMENTS IN CMOS TECHNOLOGY
    1. 8.1. MASTER-SLAVE LATCH EXAMPLES
    2. 8.2. FLIP-FLOP EXAMPLES
    3. 8.3. CLOCKED STORAGE ELEMENTS WITH LOCAL CLOCK GATING
    4. 8.4. LOW-SWING CLOCK STORAGE ELEMENTS
    5. 8.5. DUAL-EDGE-TRIGGERED CLOCKED STORAGE ELEMENTS
    6. 8.6. SUMMARY
15. CHAPTER 9: MICROPROCESSOR EXAMPLES
    1. 9.1. CLOCKING FOR INTEL MICROPROCESSORS
    2. 9.2. SUN MICROSYSTEMS ULTRASPARC-III CLOCKING
    3. 9.3. ALPHA CLOCKING: A HISTORICAL OVERVIEW
    4. 9.4. CLOCKED STORAGE ELEMENTS IN IBM PROCESSORS
16. REFERENCES
17. INDEX