Book description
Your road map for meeting today's digital testing challenges
Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge.
There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as:
Binary Decision Diagrams (BDDs) and cycle-based simulation
Tester architectures/Standard Test Interface Language (STIL)
Practical algorithms written in a Hardware Design Language (HDL)
Fault tolerance
Behavioral Automatic Test Pattern Generation (ATPG)
The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach
Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.
Table of contents
- Cover Page
- Title Page
- Copyright
- Contents
- PREFACE
- CHAPTER 1: Introduction
-
CHAPTER 2: Simulation
- 2.1 INTRODUCTION
- 2.2 BACKGROUND
- 2.3 THE SIMULATION HIERARCHY
- 2.4 THE LOGIC SYMBOLS
- 2.5 SEQUENTIAL CIRCUIT BEHAVIOR
- 2.6 THE COMPILED SIMULATOR
- 2.7 EVENT-DRIVEN SIMULATION
- 2.8 MULTIPLE-VALUED SIMULATION
- 2.9 IMPLEMENTING THE NOMINAL-DELAY SIMULATOR
- 2.10 SWITCH-LEVEL SIMULATION
- 2.11 BINARY DECISION DIAGRAMS
- 2.12 CYCLE SIMULATION
- 2.13 TIMING VERIFICATION
- 2.14 SUMMARY
- PROBLEMS
- REFERENCES
-
CHAPTER 3: Fault Simulation
- 3.1 INTRODUCTION
- 3.2 APPROACHES TO TESTING
- 3.3 ANALYSIS OF A FAULTED CIRCUIT
- 3.4 THE STUCK-AT FAULT MODEL
- 3.5 THE FAULT SIMULATOR: AN OVERVIEW
- 3.6 PARALLEL FAULT PROCESSING
- 3.7 CONCURRENT FAULT SIMULATION
- 3.8 DELAY FAULT SIMULATION
- 3.9 DIFFERENTIAL FAULT SIMULATION
- 3.10 DEDUCTIVE FAULT SIMULATION
- 3.11 STATISTICAL FAULT ANALYSIS
- 3.12 FAULT SIMULATION PERFORMANCE
- 3.13 SUMMARY
- PROBLEMS
- REFERENCES
- CHAPTER 4: Automatic Test Pattern Generation
- CHAPTER 5: Sequential Logic Test
-
CHAPTER 6: Automatic Test Equipment
- 6.1 INTRODUCTION
- 6.2 BASIC TESTER ARCHITECTURES
- 6.3 THE STANDARD TEST INTERFACE LANGUAGE
- 6.4 USING THE TESTER
- 6.5 THE ELECTRON BEAM PROBE
- 6.6 MANUFACTURING TEST
- 6.7 DEVELOPING A BOARD TEST STRATEGY
- 6.8 THE IN-CIRCUIT TESTER
- 6.9 THE PCB TESTER
- 6.10 THE TEST PLAN
- 6.11 VISUAL INSPECTION
- 6.12 TEST COST
- 6.13 SUMMARY
- PROBLEMS
- REFERENCES
- CHAPTER 7: Developing a Test Strategy
- CHAPTER 8: Design-For-Testability
- CHAPTER 9: Built-In Self-Test
- CHAPTER 10: Memory Test
- CHAPTER 11: IDDQ
-
CHAPTER 12: Behavioral Test and Verification
- 12.1 INTRODUCTION
- 12.2 DESIGN VERIFICATION: AN OVERVIEW
- 12.3 SIMULATION
- 12.4 MEASURING SIMULATION THOROUGHNESS
- 12.5 RANDOM STIMULUS GENERATION
- 12.6 THE BEHAVIORAL ATPG
- 12.7 THE SEQUENTIAL CIRCUIT TEST SEARCH SYSTEM (SCIRTSS)
- 12.8 THE TEST DESIGN EXPERT
- 12.9 DESIGN VERIFICATION
- 12.10 SUMMARY
- PROBLEMS
- REFERENCES
- INDEX
Product information
- Title: Digital Logic Testing and Simulation, 2nd Edition
- Author(s):
- Release date: July 2003
- Publisher(s): Wiley-Interscience
- ISBN: 9780471439950
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