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Digital Logic Testing and Simulation, 2nd Edition

Book Description

Your road map for meeting today's digital testing challenges

Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge.

There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as:

  • Binary Decision Diagrams (BDDs) and cycle-based simulation

  • Tester architectures/Standard Test Interface Language (STIL)

  • Practical algorithms written in a Hardware Design Language (HDL)

  • Fault tolerance

  • Behavioral Automatic Test Pattern Generation (ATPG)

  • The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach

Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Contents
  5. PREFACE
    1. THE ROADMAP
    2. PART I
    3. PART II
    4. REFERENCES
  6. CHAPTER 1: Introduction
    1. 1.1 INTRODUCTION
    2. 1.2 QUALITY
    3. 1.3 THE TEST
    4. 1.4 THE DESIGN PROCESS
    5. 1.5 DESIGN AUTOMATION
    6. 1.6 ESTIMATING YIELD
    7. 1.7 MEASURING TEST EFFECTIVENESS
    8. 1.8 THE ECONOMICS OF TEST
    9. 1.9 CASE STUDIES
    10. 1.10 SUMMARY
    11. PROBLEMS
    12. REFERENCES
  7. CHAPTER 2: Simulation
    1. 2.1 INTRODUCTION
    2. 2.2 BACKGROUND
    3. 2.3 THE SIMULATION HIERARCHY
    4. 2.4 THE LOGIC SYMBOLS
    5. 2.5 SEQUENTIAL CIRCUIT BEHAVIOR
    6. 2.6 THE COMPILED SIMULATOR
    7. 2.7 EVENT-DRIVEN SIMULATION
    8. 2.8 MULTIPLE-VALUED SIMULATION
    9. 2.9 IMPLEMENTING THE NOMINAL-DELAY SIMULATOR
    10. 2.10 SWITCH-LEVEL SIMULATION
    11. 2.11 BINARY DECISION DIAGRAMS
    12. 2.12 CYCLE SIMULATION
    13. 2.13 TIMING VERIFICATION
    14. 2.14 SUMMARY
    15. PROBLEMS
    16. REFERENCES
  8. CHAPTER 3: Fault Simulation
    1. 3.1 INTRODUCTION
    2. 3.2 APPROACHES TO TESTING
    3. 3.3 ANALYSIS OF A FAULTED CIRCUIT
    4. 3.4 THE STUCK-AT FAULT MODEL
    5. 3.5 THE FAULT SIMULATOR: AN OVERVIEW
    6. 3.6 PARALLEL FAULT PROCESSING
    7. 3.7 CONCURRENT FAULT SIMULATION
    8. 3.8 DELAY FAULT SIMULATION
    9. 3.9 DIFFERENTIAL FAULT SIMULATION
    10. 3.10 DEDUCTIVE FAULT SIMULATION
    11. 3.11 STATISTICAL FAULT ANALYSIS
    12. 3.12 FAULT SIMULATION PERFORMANCE
    13. 3.13 SUMMARY
    14. PROBLEMS
    15. REFERENCES
  9. CHAPTER 4: Automatic Test Pattern Generation
    1. 4.1 INTRODUCTION
    2. 4.2 THE SENSITIZED PATH
    3. 4.3 THE D-ALGORITHM
    4. 4.4 TESTDETECT
    5. 4.5 THE SUBSCRIPTED D-ALGORITHM
    6. 4.6 PODEM
    7. 4.7 FAN
    8. 4.8 SOCRATES
    9. 4.9 THE CRITICAL PATH
    10. 4.10 CRITICAL PATH TRACING
    11. 4.11 BOOLEAN DIFFERENCES
    12. 4.12 BOOLEAN SATISFIABILITY
    13. 4.13 USING BDDs FOR ATPG
    14. 4.14 SUMMARY
    15. PROBLEMS
    16. REFERENCES
  10. CHAPTER 5: Sequential Logic Test
    1. 5.1 INTRODUCTION
    2. 5.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC
    3. 5.3 SEQUENTIAL TEST METHODS
    4. 5.4 SEQUENTIAL LOGIC TEST COMPLEXITY
    5. 5.5 EXPERIMENTS WITH SEQUENTIAL MACHINES
    6. 5.6 A THEORETICAL LIMIT ON SEQUENTIAL TESTABILITY
    7. 5.7 SUMMARY
    8. PROBLEMS
    9. REFERENCES
  11. CHAPTER 6: Automatic Test Equipment
    1. 6.1 INTRODUCTION
    2. 6.2 BASIC TESTER ARCHITECTURES
    3. 6.3 THE STANDARD TEST INTERFACE LANGUAGE
    4. 6.4 USING THE TESTER
    5. 6.5 THE ELECTRON BEAM PROBE
    6. 6.6 MANUFACTURING TEST
    7. 6.7 DEVELOPING A BOARD TEST STRATEGY
    8. 6.8 THE IN-CIRCUIT TESTER
    9. 6.9 THE PCB TESTER
    10. 6.10 THE TEST PLAN
    11. 6.11 VISUAL INSPECTION
    12. 6.12 TEST COST
    13. 6.13 SUMMARY
    14. PROBLEMS
    15. REFERENCES
  12. CHAPTER 7: Developing a Test Strategy
    1. 7.1 INTRODUCTION
    2. 7.2 THE TEST TRIAD
    3. 7.3 OVERVIEW OF THE DESIGN AND TEST PROCESS
    4. 7.4 A TESTBENCH
    5. 7.5 FAULT MODELING
    6. 7.6 TECHNOLOGY-RELATED FAULTS
    7. 7.7 THE FAULT SIMULATOR
    8. 7.8 BEHAVIORAL FAULT MODELING
    9. 7.9 THE TEST PATTERN GENERATOR
    10. 7.10 MISCELLANEOUS CONSIDERATIONS
    11. 7.11 SUMMARY
    12. PROBLEMS
    13. REFERENCES
  13. CHAPTER 8: Design-For-Testability
    1. 8.1 INTRODUCTION
    2. 8.2 AD HOC DESIGN-FOR-TESTABILITY RULES
    3. 8.3 CONTROLLABILITY/OBSERVABILITY ANALYSIS
    4. 8.4 THE SCAN PATH
    5. 8.5 THE PARTIAL SCAN PATH
    6. 8.6 SCAN SOLUTIONS FOR PCBs
    7. 8.7 SUMMARY
    8. PROBLEMS
    9. REFERENCES
  14. CHAPTER 9: Built-In Self-Test
    1. 9.1 INTRODUCTION
    2. 9.2 BENEFITS OF BIST
    3. 9.3 THE BASIC SELF-TEST PARADIGM
    4. 9.4 RANDOM PATTERN EFFECTIVENESS
    5. 9.5 SELF-TEST APPLICATIONS
    6. 9.6 REMOTE TEST
    7. 9.7 BLACK-BOX TESTING
    8. 9.8 FAULT TOLERANCE
    9. 9.9 SUMMARY
    10. PROBLEMS
    11. REFERENCES
  15. CHAPTER 10: Memory Test
    1. 10.1 INTRODUCTION
    2. 10.2 SEMICONDUCTOR MEMORY ORGANIZATION
    3. 10.3 MEMORY TEST PATTERNS
    4. 10.4 MEMORY FAULTS
    5. 10.5 MEMORY SELF-TEST
    6. 10.6 REPAIRABLE MEMORIES
    7. 10.7 ERROR CORRECTING CODES
    8. 10.8 SUMMARY
    9. PROBLEMS
    10. REFERENCES
  16. CHAPTER 11: IDDQ
    1. 11.1 INTRODUCTION
    2. 11.2 BACKGROUND
    3. 11.3 SELECTING VECTORS
    4. 11.4 CHOOSING A THRESHOLD
    5. 11.5 MEASURING CURRENT
    6. 11.6 I DDQ VERSUS BURN-IN
    7. 11.7 PROBLEMS WITH LARGE CIRCUITS
    8. 11.8 SUMMARY
    9. PROBLEMS
    10. REFERENCES
  17. CHAPTER 12: Behavioral Test and Verification
    1. 12.1 INTRODUCTION
    2. 12.2 DESIGN VERIFICATION: AN OVERVIEW
    3. 12.3 SIMULATION
    4. 12.4 MEASURING SIMULATION THOROUGHNESS
    5. 12.5 RANDOM STIMULUS GENERATION
    6. 12.6 THE BEHAVIORAL ATPG
    7. 12.7 THE SEQUENTIAL CIRCUIT TEST SEARCH SYSTEM (SCIRTSS)
    8. 12.8 THE TEST DESIGN EXPERT
    9. 12.9 DESIGN VERIFICATION
    10. 12.10 SUMMARY
    11. PROBLEMS
    12. REFERENCES
  18. INDEX