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Digital Logic Design, 4th Edition

Book Description

New, updated and expanded topics in the fourth edition include: EBCDIC, Grey code, practical applications of flip-flops, linear and shaft encoders, memory elements and FPGAs. The section on fault-finding has been expanded. A new chapter is dedicated to the interface between digital components and analog voltages.

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Dedication
  5. Copyright
  6. Preface to the fourth edition
  7. Acknowledgments
  8. Chapter 1: Number systems and codes
    1. 1.1 Introduction
    2. 1.2 Number systems
    3. 1.3 Conversion between number systems
    4. 1.4 Binary addition and subtraction
    5. 1.5 Signed arithmetic
    6. 1.6 Complement arithmetic
    7. 1.7 Complement representation for binary numbers
    8. 1.8 The validity of 1’s and 2’s complement arithmetic
    9. 1.9 Offset binary representation
    10. 1.10 Addition and subtraction of 2’s complement numbers
    11. 1.11 Graphical interpretation of 2’s complement representation
    12. 1.12 Addition and subtraction of 1’s complement numbers
    13. 1.13 Multiplication of unsigned binary numbers
    14. 1.14 Multiplication of signed binary numbers
    15. 1.15 Binary division
    16. 1.16 Floating point arithmetic
    17. 1.17 Binary codes for decimal digits
    18. 1.18 n-cubes and distance
    19. 1.19 Error detection and correction
    20. 1.20 The Hamming code
    21. 1.21 Gray code
    22. 1.22 The ASCII code
    23. Problems
  9. Chapter 2: Boolean algebra
    1. 2.1 Introduction
    2. 2.2 Boolean algebra
    3. 2.3 Derived Boolean operations
    4. 2.4 Boolean functions
    5. 2.5 Truth tables
    6. 2.6 The logic of a switch
    7. 2.7 The switch implementation of the AND function
    8. 2.8 The switch implementation of the OR function
    9. 2.9 The gating function of the AND and OR gates
    10. 2.10 The inversion function
    11. 2.11 Gate or switch implementation of a Boolean function
    12. 2.12 The Boolean theorems
    13. 2.13 Complete sets
    14. 2.14 The exclusive-OR (XOR) function
    15. 2.15 The Reed–Muller equation
    16. 2.16 Set theory and the Venn diagram
  10. Chapter 3: Karnaugh maps and function simplification
    1. 3.2 Introduction
    2. 3.2 Minterms and maxterms
    3. 3.3 Canonical forms
    4. 3.4 Boolean functions of two variables
    5. 3.5 The Karnaugh map
    6. 3.6 Plotting Boolean functions on a Karnaugh map
    7. 3.7 Maxterms on the Karnaugh map
    8. 3.8 Simplification of Boolean functions
    9. 3.9 The inverse function
    10. 3.10 ‘Don’t care’ terms
    11. 3.11 Simplification of products of maxterms
    12. 3.12 The Quine–McCluskey tabular simplification method
    13. 3.13 Properties of prime implicant tables
    14. 3.14 Cyclic prime implicant tables
    15. 3.15 Semi-cyclic prime implicant tables
    16. 3.16 Quine–McCluskey simplification of functions containing ‘don’t care’ terms
    17. 3.17 Decimal approach to Quine–McCluskey simplification of Boolean functions
    18. 3.18 Multiple output circuits
    19. 3.19 Tabular methods for multiple output functions
    20. 3.20 Reduced dimension maps
    21. 3.21 Plotting RDMs from truth tables
    22. 3.22 Reading RDM functions
    23. 3.23 Looping rules for RDMs
    24. 3.24 Criteria for minimisation
    25. Problems
  11. Chapter 4: Combinational logic design principles
    1. 4.1 Introduction
    2. 4.2 The NAND function
    3. 4.3 NAND logic implementation of AND and OR functions
    4. 4.4 NAND logic implementation of sums-of-products
    5. 4.5 The NOR function
    6. 4.6 NOR logic implementation of AND and OR functions
    7. 4.7 NOR logic implementation of products-of-sums
    8. 4.8 NOR logic implementation of sums-of-products
    9. 4.9 Boolean algebraic analysis of NAND and NOR networks
    10. 4.10 Symbolic circuit analysis for NAND and NOR networks
    11. 4.11 Alternative function representations
    12. 4.12 Gate signal conventions
    13. 4.13 Gate expansion
    14. 4.14 Miscellaneous gate networks
    15. 4.15 Exclusive-OR and exclusive-NOR
    16. 4.16 Noise margins
    17. 4.17 Propagation time
    18. 4.18 Speed-power products
    19. 4.19 Fan-out
    20. Problems
  12. Chapter 5: Combinational logic design with MSI circuits
    1. 5.1 Introduction
    2. 5.2 Multiplexers and data selection
    3. 5.3 Available MSI multiplexers
    4. 5.4 Interconnecting multiplexers
    5. 5.5 The multiplexer as a Boolean function generator
    6. 5.6 Multi-level multiplexing
    7. 5.7 Demultiplexers
    8. 5.8 Multiplexer/demultiplexer data transmission system
    9. 5.9 Decoders
    10. 5.10 Decoder networks
    11. 5.11 The decoder as a minterm generator
    12. 5.12 Display decoding
    13. 5.13 Encoder circuit principles
    14. 5.14 Available MSI encoders
    15. 5.15 Encoding networks
    16. 5.16 Parity generation and checking
    17. 5.17 Digital comparators
    18. 5.18 Iterative circuits
  13. Chapter 6: Latches and flip-flops
    1. 6.1 Introduction
    2. 6.2 The bistable element
    3. 6.3 The SR latch
    4. 6.4 The controlled SR latch
    5. 6.5 The controlled D latch
    6. 6.6 Latch timing parameters
    7. 6.7 The JK flip-flop
    8. 6.8 The master/slave JK flip-flop
    9. 6.9 Asynchronous controls (direct preset and clear)
    10. 6.10 1’s and 0’s catching
    11. 6.11 The master/slave SR flip-flop
    12. 6.12 The edge-triggered D flip-flop
    13. 6.13 The edge-triggered JK flip-flop
    14. 6.14 The T flip-flop
    15. 6.15 Mechanical switch debouncing
    16. 6.16 Registers
    17. Problems
  14. Chapter 7: Counters and registers
    1. 7.1 Introduction
    2. 7.2 The clock signal
    3. 7.3 Basic counter design
    4. 7.4 Series and parallel connection of counters
    5. 7.5 Scale-of-five up-counter
    6. 7.6 The design steps for a synchronous counter
    7. 7.7 Gray code counters
    8. 7.8 Design of decade Gray code up-counter
    9. 7.9 Scale-of-16 up/down counter
    10. 7.10 Asynchronous binary counters
    11. 7.11 Decoding of asynchronous counters
    12. 7.12 Asynchronous resettable counters
    13. 7.13 Integrated circuit counters
    14. 7.14 Cascading of IC counter chips
    15. 7.15 Shift registers
    16. 7.16 The 4-bit 7494 shift register
    17. 7.17 The 4-bit 7495 universal shift register
    18. 7.18 The 74165 parallel loading 8-bit shift register
    19. 7.19 The use of shift registers as counters and sequence generators
    20. 7.20 The universal state diagram for shift registers
    21. 7.21 The design of a decade counter
    22. 7.22 The ring counter
    23. 7.23 The twisted ring or Johnson counter
    24. 7.24 Series and parallel interconnection of Johnson counters
    25. 7.25 Shift registers with XOR feedback
    26. 7.26 Multi-bit rate multipliers
    27. Problems
  15. Chapter 8: Clock-driven sequential circuits
    1. 8.1 Introduction
    2. 8.2 The basic synchronous sequential circuit
    3. 8.3 Analysis of a clocked sequential circuit
    4. 8.4 Design steps for synchronous sequential circuits
    5. 8.5 The design of a sequence detector
    6. 8.6 The Moore and Mealy state machines
    7. 8.7 Analysis of a sequential circuit implemented with JK flip-flops
    8. 8.8 Sequential circuit design using JK flip-flops
    9. 8.9 State reduction
    10. 8.10 State assignment
    11. 8.11 Algorithmic state machine charts
    12. 8.12 Conversion of an ASM chart into hardware
    13. 8.13 The ‘one-hot’ state assignment
    14. 8.14 Clock skew
    15. 8.15 Clock timing constraints
    16. 8.16 Asynchronous inputs
    17. 8.17 The handshake
    18. Problems
  16. Chapter 9: Event driven circuits
    1. 9.1 Introduction
    2. 9.2 Design procedure for asynchronous sequential circuits
    3. 9.3 Stable and unstable states
    4. 9.4 Design of a lamp switching circuit
    5. 9.5 Races
    6. 9.6 Race free assignments
    7. 9.7 The pump problem
    8. 9.8 Design of a sequence detector
    9. 9.9 State reduction for incompletely specified machines
    10. 9.10 Compatibility
    11. 9.11 Determination of compatible pairs
    12. 9.12 The merger diagram
    13. 9.13 The state reduction procedure
    14. 9.14 Circuit hazards
    15. 9.15 Gate delays
    16. 9.16 The generation of spikes
    17. 9.17 The generation of static hazards in combinational networks
    18. 9.18 The elimination of static hazards
    19. 9.19 Design of hazard-free combinational networks
    20. 9.20 Detection of hazards in an existing network
    21. 9.21 Hazard-free asynchronous circuit design
    22. 9.22 Dynamic hazards
    23. 9.23 Function hazards
    24. 9.24 Essential hazards
  17. Chapter 10: Instrumentation and interfacing
    1. 10.1 Introduction
    2. 10.2 Schmitt trigger circuits
    3. 10.3 Schmitt input gates
    4. 10.4 Digital-to-analogue conversion
    5. 10.5 Analogue-to-digital conversion
    6. 10.6 Flash converters
    7. 10.7 Integrating A/D converter types
    8. 10.8 A/D converter types using an embedded D/A converter
    9. 10.9 Shaft encoders and linear encoders
    10. 10.10 Sensing of motion
    11. 10.11 Absolute encoders
    12. 10.12 Conversion from Gray code to base 2
    13. 10.13 Petherick code
    14. 10.14 Incremental encoders
    15. 10.15 Open collector and tri-state gates
    16. 10.16 Use of open collector gates
    17. 10.17 Use of tri-state buffers and gates
    18. 10.18 Other interfacing components
    19. Problems
  18. Chapter 11: Programmable logic devices
    1. 11.1 Introduction
    2. 11.2 Read only memory
    3. 11.3 ROM timing
    4. 11.4 Internal ROM structure
    5. 11.5 Implementation of Boolean functions using ROMs
    6. 11.7 Memory addressing
    7. 11.8 Design of sequential circuits using ROMs
    8. 11.9 Programmable logic devices (PLDs)
    9. 11.10 Programmable gate arrays (PGAs)
    10. 11.11 Programmable logic arrays (PLAs)
    11. 11.12 Programmable array logic (PAL)
    12. 11.13 Programmable logic sequencers (PLSs)
    13. 11.14 Field programmable gate arrays (FPGAs)
    14. 11.15 Xilinx field programmable gate arrays
    15. 11.16 Actel programmable gate arrays
    16. 11.17 Altera erasable programmable logic devices
    17. Problems
  19. Chapter 12: Arithmetic circuits
    1. 12.1 Introduction
    2. 12.2 The half adder
    3. 12.3 The full adder
    4. 12.4 Binary subtraction
    5. 12.5 The 4-bit binary full adder
    6. 12.6 Carry look-ahead addition
    7. 12.7 The 74283 4-bit carry look-ahead adder
    8. 12.8 Addition/subtraction circuits using complement arithmetic
    9. 12.9 Overflow
    10. 12.10 Serial addition and subtraction
    11. 12.11 Accumulating adder
    12. 12.12 Decimal arithmetic with MSI adders
    13. 12.13 Adder/subtractor for decimal arithmetic
    14. 12.14 The 7487 true/complement unit
    15. 12.15 Arithmetic/logic unit design
    16. 12.16 Available MSI arithmetic/logic units
    17. 12.17 Multiplication
    18. 12.18 Combinational multipliers
    19. 12.19 ROM implemented multiplier
    20. 12.20 The shift and add multiplier
    21. 12.21 Available multiplier packages
    22. 12.22 Signed arithmetic
    23. 12.23 Booth’s algorithm
    24. 12.24 Implementation of Booth’s algorithm
  20. Chapter 13: Fault diagnosis and testing
    1. 13.1 Introduction
    2. 13.2 Fault detection and location
    3. 13.3 Gate sensitivity
    4. 13.4 A fault test for a 2-input AND gate
    5. 13.5 Path sensitisation
    6. 13.6 Path sensitisation in networks with fan-out
    7. 13.7 Undetectable faults
    8. 13.8 Bridging faults
    9. 13.9 The fault detection table
    10. 13.10 Two-level circuit fault detection in AND/OR circuits
    11. 13.11 Two-level circuit fault detection in OR/AND circuits
    12. 13.12 Boolean difference
    13. 13.13 Compact testing techniques
    14. 13.14 Signature analysis
    15. 13.15 The scan path testing technique
    16. 13.16 Designing for testability
    17. I. Problems
  21. Appendix Functional logic symbols
  22. Answers to problems
  23. Bibliography
  24. Index