Digital Interface Design and Application

List of Figures

Figure 1.1 Fundamental computer architecture

Figure 1.2 Interface software structure

Figure 1.3 Cross-coupled flip/flop circuit

Figure 1.4 Uncoupled circuit

Figure 1.5 D-type edge-triggered latch

Figure 1.6 Timing diagram

Figure 1.7 Flip/flop with enable functionality

Figure 1.8 Four-bit register with group input enable IE and group output enable OE

Figure 1.9 Push/pull output driver

Figure 1.10 Wired-AND connection of multiple outputs

Figure 1.11 Full address decode example

Figure 1.12 Partial address decode

Figure 1.13 Block decode

Figure 1.14 Screen-shot for uVision4 IDE

Figure 1.15 IDE management window

Figure 2.1 Fundamental processor structure

Figure 2.2 Bus timing relationships

Figure 2.3 Basic latch

Figure 2.4 A simple output interface

Figure 2.5 Simple decode for output

Figure 2.6 A tri-state buffer

Figure 2.7 A simple input interface circuit

Figure 2.8 Combined I/O

Figure 2.9 GPIO pin circuit

Figure 2.10 Observed code output pattern

Figure 2.11 16 -key matrix keyboard

Figure 2.12 Keyboard interface connections

Figure 2.13 Timing diagram for keyboard interface

Figure 3.1 A simple timer function

Figure 3.2 The simplified timer architecture

Figure 3.3 Upward count mode

Figure 3.4 Downward count mode

Figure 3.5 Centre aligned mode

Figure 3.6 Timing diagram for example code

Figure 3.7 Capture/compare input circuit

Figure 3.8 Simplified timers

Figure 3.9 A PWM signal set at 40%

Figure 3.10 Servo control with PWM

Figure 3.11 Servo controller circuit diagram ...