Digital Integrated Circuit Design Using Verilog and Systemverilog

Appendix A

SystemVerilog keywords

The following are the reserved words per IEEE Standard 1800. Although not all will be implemented in all design automation tools, none should be used for identifiers.

Verilog is case sensitive. To be recognized as a keyword, these words must be all lower case. The code in Figure A.1 uses capitalized keywords as identifiers. Any temptation to use this technique should be resisted.

Figure A.1 Legal but awkward use of capitalized keywords as identifiers

accept_on

alias

always

always_comb

always_ff

always_latch

and

assert

assign

assume

automatic

before

begin

bind

bins

binsof

bit

break

buf

bufif0

bufif1