Designing SOCs with Configured Cores

14.4. Accelerating the Fast Fourier Transform

The heart of the decimation-in-frequency FFT algorithm is the “butterfly” operation, which resides at the algorithm’s innermost loop. Each butterfly operation requires six additions and four multiplications to compute the real and imaginary components of a radix-2 butterfly result. Using the TIE language, it’s possible for a design team to augment the Xtensa processor’s pipeline with four adders and two multipliers so that the processor can compute half of an FFT butterfly in one cycle.

The Xtensa processor’s configurable memory interfaces can be configured to be as wide as 128 bits so that all four real and imaginary integer input terms for each butterfly can be loaded into special-purpose FFT input ...