13.6. GALS On-Chip Networks
GALS (globally asynchronous, locally synchronous) NoCs address another growing problem in SOC design—one noted by the ITRS. There’s no escaping the conclusion laid down by the ITRS:
. . . as it becomes impossible to move signals across a large die within one clock cycle or in a power-effective manner, or to run control and dataflow processes at the same rate [best effort versus guaranteed service], the likely result is a shift to [an] asynchronous (or, globally asynchronous and locally synchronous (GALS)) design style.
This statement melds two SOC design problems: maintaining a constant clock skew across a large chip and efficiently conveying best-effort and guaranteed-service traffic among many blocks in a complex ...
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