6.12. 16-bit Multiply and Multiply/Accumulate Instructions
The 212GP, 232L, and 570T Diamond processor cores implement the 16-bit multiply and 16/32-bit multiply/accumulate instructions listed in Tables 6.9 and 6.10, respectively. The 16-bit multiply instructions use the general-purpose register file entries as sources and destinations.
| Instruction mnemonic | Instruction definition |
|---|---|
| MUL16S | 16-bit, two’s-complement multiply with 32-bit result. |
| MUL16U | 16-bit, unsigned multiply with 32-bit result. |
| Instruction mnemonic | Instruction definition |
|---|---|
| LDDEC | Load MAC16 data register with auto decrement. |
| LDINC | Load MAC16 data register with auto increment. |
| UMUL.AA.qq | Unsigned multiply ... |
Get Designing SOCs with Configured Cores now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
