5.8. SOC Connection Topologies
The large number and variety of interfaces on Xtensa and Diamond Standard Series processor cores creates a very wide architectural-design space. The PIF, local memory, and XLMI buses support all of the system topologies shown in Figures 5.1–5.5. In addition, the large number of buses, ports, and queues available on Xtensa and Diamond processor cores allows these processors to be employed in many novel system architectures that provide much higher I/O bandwidth than was previously possible with conventional microprocessor-based designs.
Get Designing SOCs with Configured Cores now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
