4.4. Basics of TIE
The TIE language takes processor configurability to a much higher level. Using TIE’s Verilog-like descriptions, a hardware or software SOC designer can enhance the basic Xtensa architecture in three significant ways:
New registers and register files that precisely match native application data types.
New instructions that operate on the existing registers and general-purpose register file and on any new registers and register files.
New, high-speed I/O ports directly into and out of the processor’s execution units.
The ability to create new instructions, registers, and register files that precisely meet the native needs of an algorithm’s operations and data types can greatly reduce the number of processor cycles required to execute ...
Get Designing SOCs with Configured Cores now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
