Designing SOCs with Configured Cores

1.7. I/O Bandwidth and Processor Core Clock Rate

This dichotomy is a significant point of difference between processor chips and processor cores. A processor core’s ability to support multiple simultaneous I/O transactions on several buses profoundly expands the possibilities for high-performance system architectures and topologies that would be uneconomical or impossible using packaged processor ICs for board-level system designs. Consequently, SOC designers should not feel the same pressures to pursue processors with high clock rates that PC designers use to achieve performance goals.

However, entrenched system-design habits and rules of thumb developed from the industry’s 35 years of collective, microprocessor-based, board-level system-design ...