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Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores

Book Description

Microprocessor cores used for SOC design are the direct descendents of Intel's original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid. Processor cores for SOC designs can be far more plastic than microprocessor ICs for board-level system designs. Shaping these cores for specific applications produces much better processor efficiency and much lower system clock rates. Together, Tensilica's Xtensa and Diamond processor cores constitute a family of software-compatible microprocessors covering an extremely wide performance range from simple control processors, to DSPs, to 3-way superscalar processors. Yet all of these processors use the same software-development tools so that programmers familiar with one processor in the family can easily switch to another. This book emphasizes a processor-centric MPSOC (multiple-processor SOC) design style shaped by the realities of the 21st-century and nanometer silicon. It advocates the assignment of tasks to firmware-controlled processors whenever possible to maximize SOC flexibility, cut power dissipation, reduce the size and number of hand-built logic blocks, shrink the associated verification effort, and minimize the overall design risk.

Table of Contents

  1. Copyright
  2. In Praise of Designing SOCs with Configured Cores...
  3. About the Author
  4. The Morgan Kaufmann Series in Systems on Silicon
  5. Foreword
  6. Preface
  7. Acknowledgements
  8. Introduction to 21st-Century SOC Design
    1. The Start of Something Big
    2. Few Pins = Massive Multiplexing
    3. Third Time’s a Charm
    4. The Microprocessor: A Universal System Building Block
    5. The Consequences of Performance—in the Macro World
    6. Increasing Processor Performance in the Micro World
    7. I/O Bandwidth and Processor Core Clock Rate
    8. Multitasking and Processor Core Clock Rate
    9. System-Design Evolution
    10. Heterogeneous- and Homogeneous-Processor System-Design Approaches
    11. The Rise of MPSOC Design
    12. Veering Away from Processor Multitasking in SOC Design
    13. Processors: The Original, Reusable Design Block
    14. A Closer Look at 21st-Century Processor Cores for SOC Design
    15. Bibliography
  9. The SOC Design Flow
    1. System-Design Goals
    2. The ASIC Design Flow
    3. The ad-hoc SOC Design Flow
    4. A Systematic MPSOC Design Flow
    5. Computational Alternatives
    6. Communication Alternatives
    7. Cycle-Accurate System Simulation
    8. Detailed Implementation
    9. Summary: Handling SOC Complexity
    10. Bibliography
  10. Xtensa Architectural Basics
    1. Introduction to Configurable Processor Architectures
    2. Xtensa Registers
    3. Register Windowing
    4. The Xtensa Program Counter
    5. Memory Address Space
    6. Bit and Byte Ordering
    7. Base Xtensa Instructions
    8. Benchmarking the Xtensa Core ISA
    9. Bibliography
  11. Basic Processor Configurability
    1. Processor Generation
    2. Xtensa Processor Block Diagram
    3. Pre-Configured Processor Cores
    4. Basics of TIE
    5. TIE Instructions
    6. Improving Application Performance Using TIE
    7. TIE Registers and Register Files
    8. TIE Ports
    9. TIE Queue Interfaces
    10. Combining Instruction Extensions with Queues
    11. Diamond Standard Series Processor Cores—Dealing with Complexity
    12. Bibliography
  12. MPSOC System Architectures and Design Tools
    1. SOC Architectural Evolution
    2. The Consequences of Architectural Evolution
    3. Memory Interfaces
    4. Memory Caches
    5. Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF
    6. The PIF
    7. Ports and Queue Interfaces
    8. SOC Connection Topologies
    9. Shared-Memory Topologies
    10. Direct Port-Connected Topologies
    11. Queue-Based System Topologies
    12. Existing Design Tools for Complex SOC Designs
    13. MPSOC Architectural-Design Tools
    14. Platform Design
    15. An MPSOC-Design Tool
    16. MPSOC System-Level Simulation Example
    17. SOC Design in the 21st Century
    18. Bibliography
  13. Introduction to Diamond Standard Series Processor Cores
    1. The Diamond Standard Series of 32-bit Processor Cores
    2. Diamond Standard Series Software-Development Tools
    3. Diamond Standard Series Feature Summary
    4. Diamond Standard Series Processor Core Hardware Overview and Comparison
    5. Diamond-Core Local-Memory Interfaces
    6. The PIF Main Bus
    7. Diamond-Core Ports and Queues
    8. Diamond Standard Series Core Instructions
    9. Zero-Overhead Loop Instructions
    10. Miscellaneous Instructions
    11. Synchronization Instructions
    12. 16-bit Multiply and Multiply/Accumulate Instructions
    13. 32-bit Multiply Instructions
    14. Diamond-Development Tools
    15. Other Specialized Diamond Standard Series Processor Instructions
    16. Choosing a Diamond
    17. Bibliography
  14. The Diamond Standard Series 108Mini Processor Core
    1. The Configurable Processor as Controller
    2. Diamond 108Mini Processor Core Interfaces
    3. The Diamond RPU
    4. Direct Input and Output Ports
    5. System Design with Diamond 108Mini Processor Cores
    6. Low-Power System Design and Operation
    7. Bibliography
  15. The Diamond 212GP Controller Core
    1. A General-Purpose Processor Core
    2. Diamond 212GP Controller Core Interfaces
    3. The XLMI Port
    4. The Diamond 212GP Processor Memory Map
    5. The 212GP RPU
    6. Direct Input and Output Ports
    7. The Diamond 212GP Controller’s Cache Interfaces
    8. System Design with the Diamond 212GP Processor Core
    9. Bibliography
  16. The Diamond 232L CPU Core
    1. The Diamond 232L: A Full-Featured CPU Core
    2. Diamond 232L CPU Core Interfaces
    3. The Diamond 232L CPU Memory Map
    4. The Diamond 232L Cache Interfaces
    5. The Diamond 232L MMU
    6. Privilege Levels and Rings
    7. System Design with the Diamond 232L CPU Core
    8. Bibliography
  17. The Diamond 570T Superscalar CPU Core
    1. The Diamond 570T: A High-Performance CPU Core
    2. Diamond 570T CPU Core Interfaces
    3. The Diamond 570T CPU Memory Map
    4. The Diamond 570T CPU’s Cache Interfaces
    5. The Diamond 570T CPU’s RPU
    6. Direct Input and Output Ports
    7. Input and Output Queue Interfaces
    8. System Design with the Diamond 570T CPU Core
    9. Bibliography
  18. The Diamond 330HiFi audio DSP Core
    1. 300 Instructions Boost Audio Performance
    2. The Diamond 330HiFi: A High-Performance audio DSP Core
    3. Diamond 330HiFi audio DSP Core Interfaces
    4. The Diamond 330HiFi audio DSP Core’s Memory Map
    5. The Diamond 330HiFi audio DSP Core’s Cache Interfaces
    6. The Diamond 330HiFi audio DSP Core’s (Region-Protection Unit)
    7. Input- and Output-Queue Interfaces
    8. System Design with the Diamond 330HiFi audio DSP Core
    9. Bibliography
  19. The Diamond 545CK DSP Core
    1. The Diamond 545CK DSP Core’s Instruction Format
    2. A High-Performance DSP Core
    3. Diamond 545CK DSP Core Interfaces
    4. The Diamond 545CK DSP Core’s Memory Map
    5. The Diamond 545CK DSP Core’s Region-Protection Unit
    6. Input- and Output-Queue Interfaces
    7. System Design with the Diamond 545CK DSP Core
    8. Bibliography
  20. Using Fixed Processor Cores in SOC Designs
    1. Toward a 21st-Century SOC Design Strategy
    2. The ITRS Proposal for SOC Design
    3. On-Chip Communications for SOCs
    4. NoC
    5. The Three NoC Temptations
    6. GALS On-Chip Networks
    7. Software Considerations for MPSOCs
    8. Bibliography
  21. Beyond Fixed Cores
    1. A Viable Alternative to Manual RTL Design and Verification
    2. The Conventional, Embedded Software-Development Flow
    3. Fit the Processor to the Algorithm
    4. Accelerating the Fast Fourier Transform
    5. Accelerating an MPEG-4 Decoder
    6. Boost Throughput with Multiple Operations per Cycle
    7. High-Speed I/O for Processor-Based Function Blocks
    8. The Single-Bus Bottleneck
    9. Alone, Faster is Not Necessarily Better
    10. Bibliography
  22. The Future of SOC Design
    1. Grand Challenges and Disaster Scenarios
      1. SOC Disaster Scenario 1: Insufficient Productivity
      2. SOC Disaster Scenario 2: Excessive System Power Dissipation
      3. SOC Disaster Scenario 3: Loss of Manufacturability
      4. SOC Disaster Scenario 4: Excessive Signal Interference
      5. SOC Disaster Scenario 5: Deteriorating Chip Reliability
    2. Avoiding the SOC Disaster Scenarios
      1. Avoiding Disaster Scenario 1: Insufficient Productivity
      2. Avoiding Disaster Scenario 2: Excessive System Power Dissipation
      3. Avoiding Disaster Scenario 3: Loss of Manufacturability
      4. Avoiding Disaster Scenario 4: Excessive Signal Interference
      5. Avoiding Disaster Scenario 5: Deteriorating Chip Reliability
    3. System-Level Design Challenges
    4. The Future Direction of SOC Design
    5. Systolic Processing
    6. Cluster Computing and NoCs
    7. The Research Accelerator for Multiple Processors Project
    8. 21st-Century SOC Design
    9. Bibliography