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Design and Test Technology for Dependable Systems-on-Chip

Book Description

Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences. Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined “classical” design and test topics and solutions for IC test technology and fault-tolerant systems.

Table of Contents

  1. Cover
  2. Title Page
  3. Copyright Page
  4. Editorial Advisory Board and List of Reviewers
    1. EDITORIAL ADVISORY BOARD
    2. LIST OF REVIEWERS
  5. Foreword
  6. Preface
    1. ORGANIZATION OF THE BOOK
    2. SECTION 4
  7. Section 1: Design, Modeling and Verification
    1. Chapter 1: System-Level Design of NoC-Based Dependable Embedded Systems
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND AND RELATED WORK
      4. SCHEDULING FRAMEWORK OF NETWORK-ON-CHIP BASED SYSTEMS
      5. CONCLUSION
    2. Chapter 2: Synthesis of Flexible Fault-Tolerant Schedules for Embedded Systems with Soft and Hard Timing Constraints
      1. ABSTRACT
      2. INTRODUCTION
      3. APPLICATION MODEL
      4. SINGLE-SCHEDULE VS. MULTIPLE-SCHEDULE QUASI-STATIC SCHEDULING
      5. SCHEDULING WITH PREEMPTION
      6. PROBLEM FORMULATION
      7. SCHEDULING STRATEGY AND ALGORITHMS
      8. EXPERIMENTAL RESULTS
      9. CONCLUSION
    3. Chapter 3: Optimizing Fault Tolerance for Multi-Processor System-on-Chip
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. JOB-LEVEL OPTIMIZATION
      4. 3. SYSTEM-LEVEL OPTIMIZATION
      5. 4. PROBABILITY ESTIMATION TECHNIQUES FOR OPTIMIZING ROLL-BACK RECOVERY WITH CHECKPOINTING
      6. 5. SUMMARY
    4. Chapter 4: Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. DECISION DIAGRAMS AND DIGITAL TEST
      5. MODELING DIGITAL CIRCUITS WITH MULTIPLE INPUT SSBDDS
      6. MODELING DIGITAL SYSTEMS WITH HIGH LEVEL DECISION DIAGRAMS
      7. SYNTHESIS OF HIGH-LEVEL DECISION DIAGRAMS FROM THE NETWORK OF COMPONENTS
      8. SYNTHESIS OF HIGH-LEVEL DECISION DIAGRAMS FROM PROCEDURAL DESCRIPTIONS
      9. VECTOR HIGH-LEVEL DECISION DIAGRAMS
      10. FUNCTIONAL FAULT MODELING IN DIGITAL SYSTEMS
      11. CONCLUSION
    5. Chapter 5: Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
      1. ABSTRACT
      2. 1 INTRODUCTION
      3. 3 FORMAL HARDWARE VERIFICATION USING BOUNDED MODEL CHECKING
      4. 4 DEBUGGING
      5. 5 COVERAGE ANALYSIS
      6. 6 CONCLUSION
  8. Section 2: Faults, Compensation and Repair
    1. Chapter 6: Advanced Technologies for Transient Faults Detection and Compensation
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. BACKGROUND
      4. 3. MITIGATION TECHNIQUES
      5. 4. CONCLUSION
    2. Chapter 7: Memory Testing and Self-Repair
      1. ABSTRACT
      2. INTRODUCTION
      3. MEMORY FAULT MODELS, TEST AND BIST
      4. BUILT-IN SELF-REPAIR
      5. FUTURE RESEARCH DIRECTIONS
      6. CONCLUSION
    3. Chapter 8: Fault-Tolerant and Fail-Safe Design Based on Reconfiguration
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND TO FAULT TOLERANT AND ON-LINE TESTING TECHNIQUES
      4. FAULT TOLERANT DESIGN TECHNIQUE WITH TOTALLY SELF-CHECKING PROPERTY
      5. FUTURE RESEARCH
      6. CONCLUSION
    4. Chapter 9: Self-Repair Technology for Global Interconnects on SoCs
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. SELF REPAIR
      5. FUTURE RESEARCH DIRECTIONS
      6. CONCLUSION
    5. Chapter 10: Built-in Self Repair for Logic Structures
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. SELF REPAIR TECHNOLOGY
      5. FUTURE RESEARCH DIRECTIONS
      6. CONCLUSION
    6. Chapter 11: Self-Repair by Program Reconfiguration in VLIW Processor Architectures
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. SELF-REPAIR BY PROGRAM RECONFIGURATION
      5. SCALABLE ALGORITHMS
      6. FUTURE RESEARCH DIRECTIONS
      7. CONCLUSION
  9. Section 3: Fault Simulation and Fault Injection
    1. Chapter 12: Fault Simulation and Fault Injection Technology Based on SystemC
      1. ABSTRACT
      2. INTRODUCTION
      3. FAULT SIMULATION AND FAULT INJECTION
      4. SYSTEMC
      5. SIMULATION OF FAULTS WITH SYSTEMC
      6. ABSTRACTION LEVELS AND FAULT MODELS
      7. THE SIMULATED FAULT INJECTION IN SYSTEMC
      8. ACCELERATION OF FAULT SIMULATION
      9. FAULT INJECTION PLATFORMS FOR SYSTEMC
      10. CONCLUSION
    2. Chapter 13: High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis
      1. ABSTRACT
      2. INTRODUCTION
      3. 2 DECISION DIAGRAM MODELS
      4. 3 HLDD SIMULATION FOR DESIGN ERROR DIAGNOSIS
      5. 4 MALICIOUS FAULT LIST GENERATION USING HLDD
      6. CONCLUSION
    3. Chapter 14: High-Speed Logic Level Fault Simulation
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. APPROACHES TO SPEED-UP THE FAULT SIMULATION
      5. EXPERIMENTAL RESULTS
      6. CONCLUSIONS
  10. Section 4: Test Technology for Systems-On-Chip
    1. Chapter 15: Software-Based Self-Test of Embedded Microprocessors
      1. ABSTRACT
      2. INTRODUCTION
      3. SOFTWARE-BASED SELF-TEST GENERATION TECHNIQUES
      4. SELF-TEST APPLICATION PROCEDURES
      5. AN EXAMPLE OF APPLICATION
      6. EVOLUTIONARY TOOL DESCRIPTION
      7. EXPERIMENTAL RESULTS
      8. I-IP SUPPORTING SBST
      9. SUMMARY
    2. Chapter 16: SoC Self Test Based on a Test-Processor
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. EMBEDDED TEST TECHNOLOGYBASED ON A TEST PROCESSOR
      5. TESTING THE TEST PROCESSOR
      6. TEST PROCESSOR IN A WATCHDOG ARCHITECTURE
      7. FUTURE RESEARCH DIRECTIONS
      8. CONCLUSION
    3. Chapter 17: Delay Faults Testing
      1. ABSTRACT
      2. INTRODUCTION
      3. DELAY FAULTS TESTING BACKGROUND
      4. CLASSIFICATION OF DELAY FAULT MODELS
      5. TEST VECTOR-PAIR APPLICATION THROUGH SCAN BASED CIRCUITS
      6. DELAY FAULTS IN ASYNCHRONOUS CIRCUITS AND THEIR TESTING
      7. FUTURE RESEARCH DIRECTIONS
      8. CONCLUSION
    4. Chapter 18: Low Power Testing
      1. ABSTRACT
      2. INTRODUCTION
      3. POWER CONSUMPTION METRICS
      4. POWER CONSUMPTION DURING TEST APPLICATION
      5. APPROXIMATION MODELS
      6. A SURVEY OF EXISTING APPROACHES TO REDUCE POWER CONSUMPTION DURING TEST APPLICATION
      7. POWER-CONSTRAINED TEST SCHEDULING METHODS
      8. CONCLUSION
    5. Chapter 19: Thermal-Aware SoC Test Scheduling
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND AND MOTIVATION
      4. MAIN FOCUS OF THE CHAPTER
      5. CONCLUSION
  11. Section 5: Test Planning, Compression and Application in SoCs
    1. Chapter 20: Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. BACKGROUND ON MODULAR TESTING
      4. 2.1. TEST-ARCHITECTURE DESIGN
      5. 3. BACKGROUND ON TEST DATA COMPRESSION
      6. 4. PROBLEM STATEMENT AND EXPERIMENTAL SETUP
      7. 5. CORE-LEVEL ANALYSIS
      8. 6. SYSTEM-LEVEL ANALYSIS
      9. 7. CONCLUSION
    2. Chapter 21: Reduction of the Transferred Test Data Amount
      1. ABSTRACT
      2. INTRODUCTION
      3. MIXED-MODE BIST APPROACHES
      4. AD-HOC TEST PATTERN COMPRESSION
      5. COMPRESSION TECHNIQUES USING SUBSIDIARY DATA FROM ATPG
      6. CONCLUSION
    3. Chapter 22: Sequential Test Set Compaction in LFSR Reseeding
      1. ABSTRACT
      2. INTRODUCTION
      3. BRIEF COMPARISON OF LOGIC BIST TECHNIQUES
      4. THE LFSR RESEEDING OPTIMIZATION FLOW AND MODEL
      5. OVERVIEW OF STATIC COMPACTION METHODS
      6. COMPACTION ALGORITHM FOR LFSR SEQUENCES
      7. EXPERIMENTAL RESULTS
      8. CONCLUSION
  12. Compilation of References
  13. About the Contributors