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Design and Modeling of Low Power VLSI Systems

Book Description

Very Large Scale Integration (VLSI) Systems refer to the latest development in computer microchips which are created by integrating hundreds of thousands of transistors into one chip. Emerging research in this area has the potential to uncover further applications for VSLI technologies in addition to system advancements. Design and Modeling of Low Power VLSI Systems analyzes various traditional and modern low power techniques for integrated circuit design in addition to the limiting factors of existing techniques and methods for optimization. Through a research-based discussion of the technicalities involved in the VLSI hardware development process cycle, this book is a useful resource for researchers, engineers, and graduate-level students in computer science and engineering.

Table of Contents

  1. Cover
  2. Title Page
  3. Copyright Page
  4. Book Series
    1. Mission
    2. Coverage
  5. Editorial Advisory Board and List of Reviewers
    1. Editorial Advisory Board
    2. List of Reviewers
  6. Preface
    1. ORGANIZATION OF THE BOOK
    2. WHO AND HOW TO READ THIS BOOK
    3. SIGNIFICANCE OF BOOK IN TODAY’S ECOSYSTEM
  7. Introduction
  8. Section 1: Fundamental of Power Aware VLSI Design
    1. Chapter 1: Low Power Design Techniques
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. BASIC METHODOLOGIES OF LOW POWER CMOS DESIGN
      4. 3. LOW POWER NANOELECTRONIC DEVICES
      5. 4. CONCLUSION
      6. REFERENCES
    2. Chapter 2: Low Power Strategies for beyond Moore's Law Era
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. LIST OF LOW POWER DEVICES
      4. 3. TUNNEL FET (TFET)
      5. 4. HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)
      6. 5. GRAPHENE
      7. 6. OTHER 2-D STRUCTURES
      8. 7. QUANTUM DOT
      9. 8. MEMRISTOR: INTRODUCTION
      10. 9. RESISTIVE RANDOM ACCESS MEMORY (RRAM)
      11. CONCLUSION
      12. REFERENCES
    3. Chapter 3: Challenges and Limitations of Low Power Techniques
      1. ABSTRACT
      2. INTRODUCTION
      3. BACKGROUND
      4. WHY LOW POWER?
      5. SOURCES OF LOW POWER
      6. CMOS LOW POWER ANALOG TECHNIQUES
      7. LEAKAGE CURRENT TECHNIQUES
      8. SUMMARY
      9. REFERENCES
    4. Chapter 4: Leakage Minimization in CMOS VLSI Circuits
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. SOURCES OF POWER DISSIPATION
      4. 3. CLASSIFICATION OF LEAKAGE CURRENTS
      5. 4. CIRCUIT LEVEL LEAKAGE MINIMIZATION TECHNIQUES
      6. 5. CONCLUSION
      7. REFERENCES
  9. Section 2: Non-Traditional Low Power Methodologies
    1. Chapter 5: Contemporary Low Power Design Approaches
      1. ABSTRACT
      2. INTRODUCTION
      3. OVERVIEW FOR BANDGAP REFERENCE CIRCUIT (BGR), VOLTAGE LEVEL SHIFTER (VLS) AND DYNAMIC COMPARATOR
      4. BANDGAP REFERENCE CIRCUIT (BGR)
      5. LEVEL SHIFTER
      6. COMPARATOR
      7. SUMMARY
      8. REFERENCES
    2. Chapter 6: Low Power VLSI Circuit Design using Energy Recovery Techniques
      1. ABSTRACT
      2. INTRODUCTION
      3. CONVENTIONAL METHODOLOGIES OF LOW POWER VLSI DESIGN AND THE CURRENT STATUS
      4. REVERSIBLE AND ADIABATIC COMPUTING FOR LOW POWER
      5. ENERGETICS OF CONVENTIONAL STATIC CMOS VS. QUASI-ADIABATIC CMOS CIRCUITS
      6. ENERGETICS OF ADIABATIC CIRCUIT
      7. THE FOUR-PHASE POWER CLOCK SOURCES
      8. QUASI-ADIABATIC LOGIC STRUCTURES
      9. PERFORMANCE METRICS OF ADIABATIC CIRCUITS
      10. LEAKAGE MODELS OF THE INVERTERS
      11. PERFORMANCE COMPARISONS AMONG THE ADIABATIC CIRCUITS
      12. CONCLUSION
      13. REFERENCES
  10. Section 3: Low Power Applications and Studies
    1. Chapter 7: State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems
      1. ABSTRACT
      2. INTRODUCTION
      3. SYNCHRONIZATION CIRCUITS IN DIGITAL SYSTEMS
      4. DYNAMIC AND STATIC LATCHES AND FLIP-FLOPS
      5. REVIEW OF STATE-OF-THE-ART FLIP-FLOPS AND PROPOSED DESIGNS
      6. SIMULATION PARAMETERS, TEST BENCH AND METHODOLOGY
      7. SIMULATION RESULTS AND DISCUSSION
      8. CONCLUSION
      9. REFERENCES
      10. KEY TERMS AND DEFINITIONS
      11. APPENDIX 1
      12. APPENDIX 2
    2. Chapter 8: Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. WEARABLE AND IMPLANTABLE MEDICAL DEVICES
      4. 3. ELECTROPHYSIOLOGICAL SIGNALS
      5. 4. A BRIEF INTRODUCTION TO THE SAR ADC
      6. 5. ADC POWER CONSUMPTION
      7. 6. INPUT-AWARE SAR ADCS
      8. 7. APPLICATIONS AND DISCUSSIONS
      9. 8. CONCLUSION
      10. REFERENCES
      11. KEY TERMS AND DEFINITIONS
      12. APPENDIX 1: LEVEL-CROSSING ADC
      13. APPENDIX 2: MATLAB/OCTAVE SOURCES
    3. Chapter 9: The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology
      1. ABSTRACT
      2. INTRODUCTION
      3. 1. TOPOLOGIES OF CMOS LNA
      4. 2. COMPARISON OF CSLNA AND CGLNA
      5. 3. IEEE 802.15.4 SPECIFICATIONS
      6. 4. ULTRA-LOW POWER CMOS LNA WITH CAPACITIVE CROSS-COUPLING TECHNIQUE
      7. CONCLUSION
      8. REFERENCES
    4. Chapter 10: Low Power Arithmetic Circuit Design for Multimedia Applications
      1. ABSTRACT
      2. 1. INTRODUCTION
      3. 2. CONCLUSION
      4. REFERENCES
    5. Chapter 11: Case Study
      1. ABSTRACT
      2. INTRODUCTION
      3. SYSTEM ON CHIP DESCRIPTION AND COMPONENTS
      4. DESIGN CONSIDERATIONS
      5. SYSTEM ON CHIP DESIGN FLOW
      6. DDFS METHODOLOGY
      7. APPLICATION PROGRAM AND USER INTERFACE
      8. IMPLEMENTATION
      9. SAMPLE APPLICATIONS
      10. CONCLUSION
      11. REFERENCES
      12. KEY TERMS AND DEFINITIONS
      13. APPENDIX
    6. Chapter 12: Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip
      1. ABSTRACT
      2. INTRODUCTION
      3. VLSI POWER CONSUMPTION AND ITS TYPES
      4. METHODOLOGY FOR DESIGNING THE LOW POWER DESIGN FOR VLSI BASED HIGH SPEED COMMUNICATION SYSTEM
      5. POWER REDUCTION AND ANALYSIS FOR 100Gb/s DPSK COMMUNICATION SYSTEM USING IO STANDARD TECHNIQUE
      6. RESULTS AND DISCUSSION
      7. CONCLUSION AND FUTURE SCOPE
      8. ACKNOWLEDGMENT
      9. REFERENCES
  11. Compilation of References
  12. About the Contributors