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Computer Systems, 4th Edition

Book Description

Completely revised and updated, Computer Systems, Fourth Edition offers a clear, detailed, step-by-step introduction to the central concepts in computer organization, assembly language, and computer architecture. Important Notice: The digital edition of this book is missing some of the images or content found in the physical edition.

Table of Contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Dedication
  5. Preface
  6. Contents
  7. Level 7 Application
    1. Chapter 1 Computer Systems
      1. 1.1 Levels of Abstraction
        1. Abstraction in Art
        2. Abstraction in Documents
        3. Abstraction in Organizations
        4. Abstraction in Machines
        5. Abstraction in Computer Systems
      2. 1.2 Hardware
        1. Input Devices
        2. Output Devices
        3. Main Memory
        4. Central Processing Unit
      3. 1.3 Software
        1. Operating Systems
        2. Software Analysis and Design
      4. 1.4 Database Systems
        1. Relations
        2. Queries
        3. Structure of the Language
      5. Summary
      6. Exercises
  8. Level 6 High-Order Language
    1. Chapter 2 C++
      1. 2.1 Variables
        1. The C++ Compiler
        2. Machine Independence
        3. The C++ Memory Model
        4. Global Variables and Assignment Statements
        5. Local Variables
      2. 2.2 Flow of Control
        1. The If/Else Statement
        2. The Switch Statement
        3. The While Loop
        4. The Do Loop
        5. Arrays and the For Loop
      3. 2.3 Functions
        1. Void Functions and Call-By-Value Parameters
        2. Functions
        3. Call-By-Reference Parameters
      4. 2.4 Recursion
        1. A Factorial Function
        2. Thinking Recursively
        3. Recursive Addition
        4. A Binomial Coefficient Function
        5. Reversing the Elements of an Array
        6. Towers of Hanoi
        7. Mutual Recursion
        8. The Cost of Recursion
      5. 2.5 Dynamic Memory Allocation
        1. Pointers
        2. Structures
        3. Linked Data Structures
      6. Summary
      7. Exercises
  9. Level 3 Instruction Set Architecture
    1. Chapter 3 Information Representation
      1. 3.1 Unsigned Binary Representation
        1. Binary Storage
        2. Integers
        3. Base Conversions
        4. Range for Unsigned Integers
        5. Unsigned Addition
        6. The Carry Bit
      2. 3.2 Two’s Complement Binary Representation
        1. Two’s Complement Range
        2. Base Conversions
        3. The Number Line
        4. The Overflow Bit
        5. The Negative and Zero Bits
      3. 3.3 Operations in Binary
        1. Logical Operators
        2. Register Transfer Language
        3. Arithmetic Operators
        4. Rotate Operators
      4. 3.4 Hexadecimal and Character Representations
        1. Hexadecimal
        2. Base Conversions
        3. Characters
      5. 3.5 Floating Point Representation
        1. Binary Fractions
        2. Excess Representations
        3. The Hidden Bit
        4. Special Values
        5. The IEEE 754 Floating Point Standard
      6. 3.6 Representations Across Levels
        1. Alternative Representations
        2. Models
      7. Summary
      8. Exercises
    2. Chapter 4 Computer Architecture
      1. 4.1 Hardware
        1. Central Processing Unit (CPU)
        2. Main Memory
        3. Input Device
        4. Output Device
        5. Data and Control
        6. Instruction Format
      2. 4.2 Direct Addressing
        1. The Stop Instruction
        2. The Load Instruction
        3. The Store Instruction
        4. The Add Instruction
        5. The Subtract Instruction
        6. The And and Or Instructions
        7. The Invert and Negate Instructions
        8. The Load Byte and Store Byte Instructions
        9. The Character Input and Ouput Instructions
      3. 4.3 von Neumann Machines
        1. The von Neumann Execution Cycle
        2. A Character Output Program
        3. von Neumann Bugs
        4. A Character Input Program
        5. Converting Decimal to ASCII
        6. A Self-Modifying Program
      4. 4.4 Programming at Level ISA3
        1. Read-Only Memory
        2. The Pep/8 Operating System
        3. Using the Pep/8 System
      5. Summary
      6. Exercises
  10. Level 5 Assembly
    1. Chapter 5 Assembly Language
      1. 5.1 Assemblers
        1. Instruction Mnemonics
        2. Pseudo-Operations
        3. The .ASCII and .END Pseudo-ops
        4. Assemblers
        5. The .BLOCK Pseudo-op
        6. The .WORD and .BYTE Pseudo-ops
        7. Using the Pep/8 Assembler
        8. Cross Assemblers
      2. 5.2 Immediate Addressing and the Trap Instructions
        1. Immediate Addressing
        2. The DECI, DECO, and BR Instructions
        3. The STRO Instruction
        4. Interpreting Bit Patterns
        5. Disassemblers
      3. 5.3 Symbols
        1. A Program with Symbols
        2. A von Neumann Illustration
      4. 5.4 Translating from Level HOL6
        1. The cout Statement
        2. Variables and Types
        3. Global Variables and Assignment Statements
        4. Type Compatibility
        5. Pep/8 Symbol Tracer
        6. The Shift and Rotate Instructions
        7. Constants and .EQUATE
        8. Placement of Instructions and Data
      5. Summary
      6. Exercises
    2. Chapter 6 Compiling to the Assembly Level
      1. 6.1 Stack Addressing and Local Variables
        1. Stack-Relative Addressing
        2. Accessing the Run-Time Stack
        3. Local Variables
      2. 6.2 Branching Instructions and Flow of Control
        1. Translating the If Statement
        2. Optimizing Compilers
        3. Translating the If/Else Statement
        4. Translating the While Loop
        5. Translating the Do Loop
        6. Translating the For Loop
        7. Spaghetti Code
        8. Flow of Control in Early Languages
        9. The Structured Programming Theorem
        10. The Goto Controversy
      3. 6.3 Function Calls and Parameters
        1. Translating a Function Call
        2. Translating Call-By-Value Parameters with Global Variables
        3. Translating Call-By-Value Parameters with Local Variables
        4. Translating Non-Void Function Calls
        5. Translating Call-By-Reference Parameters with Global Variables
        6. Translating Call-By-Reference Parameters with Local Variables
        7. Translating Boolean Types
      4. 6.4 Indexed Addressing and Arrays
        1. Translating Global Arrays
        2. Translating Local Arrays
        3. Translating Arrays Passed as Parameters
        4. Translating the Switch Statement
      5. 6.5 Dynamic Memory Allocation
        1. Translating Global Pointers
        2. Translating Local Pointers
        3. Translating Structures
        4. Translating Linked Data Structures
      6. Summary
      7. Exercises
    3. Chapter 7 Language Translation Principles
      1. 7.1 Languages, Grammars, and Parsing
        1. Concatenation
        2. Languages
        3. Grammars
        4. A Grammar for C++ Identifiers
        5. A Grammar for Signed Integers
        6. A Context-Sensitive Grammar
        7. The Parsing Problem
        8. A Grammar for Expressions
        9. A C++ Subset Grammar
        10. Context Sensitivity of C++
      2. 7.2 Finite State Machines
        1. An FSM to Parse an Identifier
        2. Simplified Finite State Machines
        3. Nondeterministic Finite State Machines
        4. Machines with Empty Transitions
        5. Multiple Token Recognizers
      3. 7.3 Implementing Finite State Machines
        1. A Table-Lookup Parser
        2. A Direct-Code Parser
        3. An Input Buffer Class
        4. A Multiple-Token Parser
      4. 7.4 Code Generation
        1. A Language Translator
        2. Parser Characteristics
      5. Summary
      6. Exercises
  11. Level 4 Operating System
    1. Chapter 8 Process Management
      1. 8.1 Loaders
        1. The Pep/8 Operating System
        2. The Pep/8 Loader
        3. Program Termination
      2. 8.2 Traps
        1. The Trap Mechanism
        2. The RETTR Instruction
        3. The Trap Handlers
        4. Trap Addressing Mode Assertion
        5. Trap Operand Address Computation
        6. The No-Operation Trap Handlers
        7. The DECI Trap Handler
        8. The DECO Trap Handler
        9. The STRO Trap Handler and OS Vectors
      3. 8.3 Concurrent Processes
        1. Asynchronous Interrupts
        2. Processes in the Operating System
        3. Multiprocessing
        4. A Concurrent Processing Program
        5. Critical Sections
        6. A First Attempt at Mutual Exclusion
        7. A Second Attempt at Mutual Exclusions
        8. Peterson’s Algorithm for Mutual Exclusion
        9. Semaphores
        10. Critical Sections with Semaphores
      4. 8.4 Deadlocks
        1. Resource Allocation Graphs
        2. Deadlock Policy
      5. Summary
      6. Exercises
    2. Chapter 9 Storage Management
      1. 9.1 Memory Allocation
        1. Uniprogramming
        2. Fixed-Partition Multiprogramming
        3. Logical Addresses
        4. Variable-Partition Multiprogramming
        5. Paging
      2. 9.2 Virtual Memory
        1. Large Program Behavior
        2. Virtual Memory
        3. Demand Paging
        4. Page Replacement
        5. Page-Replacement Algorithms
      3. 9.3 File Management
        1. Disk Drives
        2. File Abstraction
        3. Allocation Techniques
      4. 9.4 Error Detecting and Correcting Codes
        1. Error-Detecting Codes
        2. Code Requirements
        3. Single-Error-Correcting Codes
      5. 9.5 RAID Storage Systems
        1. RAID Level 0: Nonredundant Striped
        2. RAID Level 1: Mirrored
        3. RAID Levels 01 and 10: Striped and Mirrored
        4. RAID Level 2: Memory-Style ECC
        5. RAID Level 3: Bit-Interleaved Parity
        6. RAID Level 4: Block-Interleaved Parity
        7. RAID Level 5: Block-Interleaved Distributed Parity
      6. Summary
      7. Exercises
  12. Level 1 Logic Gate
    1. Chapter 10 Combinational Circuits
      1. 10.1 Boolean Algebra and Logic Gates
        1. Combinational Circuits
        2. Truth Tables
        3. Boolean Algebra
        4. Boolean Algebra Theorems
        5. Proving Complements
        6. Logic Diagrams
        7. Alternate Representations
      2. 10.2 Combinational Analysis
        1. Boolean Expressions and Logic Diagrams
        2. Truth Tables and Boolean Expressions
        3. Two-Level Circuits
        4. The Ubiquitous NAND
      3. 10.3 Combinational Design
        1. Canonical Expressions
        2. Three-Variable Karnaugh Maps
        3. Four-Variable Karnaugh Maps
        4. Dual Karnaugh Maps
        5. Don’t-Care Conditions
      4. 10.4 Combinational Devices
        1. Viewpoints
        2. Multiplexer
        3. Binary Decoder
        4. Demultiplexer
        5. Adder
        6. Adder/Subtracter
        7. Arithmetic Logic Unit
        8. Abstraction at Level LG1
      5. Summary
      6. Exercises
    2. Chapter 11 Sequential Circuits
      1. 11.1 Latches and Clocked Flip-Flops
        1. The SR Latch
        2. The Clocked SR Flip-Flop
        3. The Master–Slave SR Flip-Flop
        4. The Basic Flip-Flops
        5. The JK Flip-Flop
        6. The D Flip-Flop
        7. The T Flip-Flop
        8. Excitation Tables
      2. 11.2 Sequential Analysis and Design
        1. A Sequential Analysis Problem
        2. Preset and Clear
        3. Sequential Design
        4. A Sequential Design Problem
      3. 11.3 Computer Subsystems
        1. Registers
        2. Buses
        3. Memory Subsystems
        4. Address Decoding
        5. A Two-Port Register Bank
      4. Summary
      5. Exercises
  13. Level 2 Microcode
    1. Chapter 12 Computer Organization
      1. 12.1 Constructing a Level-ISA3 Machine
        1. The Central Processing Unit
        2. Implementing the Store Byte Instruction
        3. Implementing the Add Instruction
        4. Implementing the Load Instruction
        5. Implementing the Arithmetic Shift Right Instruction
      2. 12.2 Performance Issues
        1. The Bus Width
        2. Specialized Hardware Units
        3. Three Areas of Optimization
        4. Microcode
      3. 12.3 The MIPS Machine
        1. Load/Store Architectures
        2. The Instruction Set
        3. Cache Memories
        4. MIPS Computer Organization
        5. Pipelining
      4. 12.4 Conclusion
        1. Simplifications in the Model
        2. The Big Picture
      5. Summary
      6. Exercises
  14. Appendix Pep/8 Architecture
  15. Solutions to Selected Exercises
  16. Index