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Computer System Designs: System-on-Chip

Book Description

The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above. It begins with a global introduction, from the high-level view to the lowest common denominator (the chip itself), then moves on to the three main building blocks of an SOC (processor, memory, and interconnect). Next is an overview of what makes SOC unique (its customization ability and the applications that drive it). The final chapter presents future challenges for system design and SOC possibilities.

Table of Contents

  1. Cover
  2. Title page
  3. Copyright page
  4. PREFACE
  5. LIST OF ABBREVIATIONS AND ACRONYMS
  6. 1 Introduction to the Systems Approach
    1. 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW
    2. 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS
    3. 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE
    4. 1.4 PROCESSOR ARCHITECTURES
    5. 1.5 MEMORY AND ADDRESSING
    6. 1.6 SYSTEM-LEVEL INTERCONNECTION
    7. 1.7 AN APPROACH FOR SOC DESIGN
    8. 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY
    9. 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC
    10. 1.10 DEALING WITH DESIGN COMPLEXITY
    11. 1.11 CONCLUSIONS
  7. 2 Chip Basics: Time, Area, Power, Reliability, and Configurability
    1. 2.1 INTRODUCTION
    2. 2.2 CYCLE TIME
    3. 2.3 DIE AREA AND COST
    4. 2.4 IDEAL AND PRACTICAL SCALING
    5. 2.5 POWER
    6. 2.6 AREA–TIME–POWER TRADE-OFFS IN PROCESSOR DESIGN
    7. 2.7 RELIABILITY
    8. 2.8 CONFIGURABILITY
    9. 2.9 CONCLUSION
  8. 3 Processors
    1. 3.1 INTRODUCTION
    2. 3.2 PROCESSOR SELECTION FOR SOC
    3. 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE
    4. 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE
    5. 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING
    6. 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS
    7. 3.7 BRANCHES: REDUCING THE COST OF BRANCHES
    8. 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR
    9. 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS
    10. 3.10 VLIW PROCESSORS
    11. 3.11 SUPERSCALAR PROCESSORS
    12. 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES
    13. 3.13 CONCLUSIONS
  9. 4 Memory Design: System-on-Chip and Board-Based Systems
    1. 4.1 INTRODUCTION
    2. 4.2 OVERVIEW
    3. 4.3 SCRATCHPADS AND CACHE MEMORY
    4. 4.4 BASIC NOTIONS
    5. 4.5 CACHE ORGANIZATION
    6. 4.6 CACHE DATA
    7. 4.7 WRITE POLICIES
    8. 4.8 STRATEGIES FOR LINE REPLACEMENT AT MISS TIME
    9. 4.9 OTHER TYPES OF CACHE
    10. 4.10 SPLIT I- AND D-CACHES AND THE EFFECT OF CODE DENSITY
    11. 4.11 MULTILEVEL CACHES
    12. 4.12 VIRTUAL-TO-REAL TRANSLATION
    13. 4.13 SOC (ON-DIE) MEMORY SYSTEMS
    14. 4.14 BOARD-BASED (OFF-DIE) MEMORY SYSTEMS
    15. 4.15 SIMPLE DRAM AND THE MEMORY ARRAY
    16. 4.16 MODELS OF SIMPLE PROCESSOR–MEMORY INTERACTION
    17. 4.17 CONCLUSIONS
  10. 5 Interconnect
    1. 5.1 INTRODUCTION
    2. 5.2 OVERVIEW: INTERCONNECT ARCHITECTURES
    3. 5.3 BUS: BASIC ARCHITECTURE
    4. 5.4 SOC STANDARD BUSES
    5. 5.5 ANALYTIC BUS MODELS
    6. 5.6 BEYOND THE BUS: NOC WITH SWITCH INTERCONNECTS
    7. 5.7 SOME NOC SWITCH EXAMPLES
    8. 5.8 LAYERED ARCHITECTURE AND NETWORK INTERFACE UNIT
    9. 5.9 EVALUATING INTERCONNECT NETWORKS
    10. 5.10 CONCLUSIONS
  11. 6 Customization and Configurability
    1. 6.1 INTRODUCTION
    2. 6.2 ESTIMATING EFFECTIVENESS OF CUSTOMIZATION
    3. 6.3 SOC CUSTOMIZATION: AN OVERVIEW
    4. 6.4 CUSTOMIZING INSTRUCTION PROCESSORS
    5. 6.5 RECONFIGURABLE TECHNOLOGIES
    6. 6.6 MAPPING DESIGNS ONTO RECONFIGURABLE DEVICES
    7. 6.7 INSTANCE-SPECIFIC DESIGN
    8. 6.8 CUSTOMIZABLE SOFT PROCESSOR: AN EXAMPLE
    9. 6.9 RECONFIGURATION
    10. 6.10 CONCLUSIONS
  12. 7 Application Studies
    1. 7.1 INTRODUCTION
    2. 7.2 SOC DESIGN APPROACH
    3. 7.3 APPLICATION STUDY: AES
    4. 7.4 APPLICATION STUDY: 3-D GRAPHICS PROCESSORS
    5. 7.5 APPLICATION STUDY: IMAGE COMPRESSION
    6. 7.6 APPLICATION STUDY: VIDEO COMPRESSION
    7. 7.7 FURTHER APPLICATION STUDIES
    8. 7.8 CONCLUSIONS
  13. 8 What’s Next: Challenges Ahead
    1. 8.1 INTRODUCTION
    2. I. THE FUTURE SYSTEM: AUTONOMOUS SYSTEM-ON-CHIP
    3. 8.2 OVERVIEW
    4. 8.3 TECHNOLOGY
    5. 8.4 POWERING THE ASOC
    6. 8.5 THE SHAPE OF THE ASOC
    7. 8.6 COMPUTER MODULE AND MEMORY
    8. 8.7 RF OR LIGHT COMMUNICATIONS
    9. 8.8 SENSING
    10. 8.9 MOTION, FLIGHT, AND THE FRUIT FLY
    11. II. THE FUTURE DESIGN PROCESS: SELF-OPTIMIZATION AND SELF-VERIFICATION
    12. 8.10 MOTIVATION
    13. 8.11 OVERVIEW
    14. 8.12 PRE-DEPLOYMENT
    15. 8.13 POST-DEPLOYMENT
    16. 8.14 ROADMAP AND CHALLENGES
    17. 8.15 SUMMARY
  14. APPENDIX: Tools for Processor Evaluation
  15. REFERENCES
  16. Index