Failures and Error Floors of Iterative Decoders
Bane Vasića, Shashi Kiran Chilappagarib and Dung Viet Nguyenb, aDepartment of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721, USA, bMarvell Semiconductor Inc., Santa Clara, CA 95054, USA a vasic@ece.arizona.edub shashickiran@gmail.com
Abstract
This chapter presents a study of graph substructures and corresponding error patterns involved in decoding failures on various channels under different iterative message passing and linear programming decoding algorithms. The intriguing structural dependence among these subgraphs, called trapping sets, suggests a comprehensive framework for studying the error floor performance of LDPC codes, as well as for designing ...
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