CCNA Data Center DCICT 640-916 Official Cert Guide

Cisco UCS B-series Best Practices for Populating DRAM

The Intel Nehalem microprocessor architecture fundamentally changed the server platform architecture by using a QuickPath Interconnect (QPI—high-speed point-to-point connections between processor, I/O and other subsystems) and by integrating a memory controller, delegating control of DRAM to each processor, relying on the QPI as a substitute to a typical front-side bus (FSB) to communicate with I/O devices and share memory access.

As a result, each processor or socket on the system board has “memory channels” directly connecting the processor and array of memory Dual In-line Memory Modules (DIMMs) available for that channel. These memory channels form a logical DIMM. It is important to note ...