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Built In Test for VLSI: Pseudorandom Techniques by J. Savir, W. H. McAnney, Paul H. Bardell

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Introduction to Testable Design

During the 1970s a quiet revolution occurred in the field of digital circuit testing. Before that time, testing was a manufacturing chore almost completely isolated from design—“we design it, you build and test it.” After that time, in many companies the entire responsibility for testing and test pattern generation was in the hands of the designers.

In that 10 year span, as circuit geometries became smaller and more compact the circuit densities available in a single package increased explosively. Pre-1970 circuit packages had perhaps one gate for each two or three package pins. By 1980 the gate-to-pin ratio had not only reversed but approached 20 gates per pin or worse. (At present it is not unusual to find 100 gates or more behind every pin.)

The increasing package density caused dramatic reductions in per circuit costs, but the percentage of those costs consumed by testing stubbornly increased. This effect was forced primarily by the loss of ability to control and observe internal circuit nodes as the gate-to-pin ratio worsened. In 1975, Phillip Writer of the Test Equipment Technical Support Office at the Naval Electronics Laboratory Center in San Diego coined the term “design for testability” and used it as the title of his paper (presented at ...

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