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Built In Test for VLSI: Pseudorandom Techniques

Book Description

This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Dedication
  5. Preface
  6. Contents
  7. 1: Digital Testing and the Need for Testable Designs
    1. 1.1 THE EVOLUTION OF TEST TECHNOLOGY
    2. 1.2 FAULT MODELS
    3. 1.3 STRUCTURAL AND FUNCTIONAL TESTING
    4. 1.4 ON-LINE VERSUS OFF-LINE TESTING
    5. 1.5 THE RELATIONSHIP BETWEEN DESIGN AND TEST
    6. 1.6 THE RELATIONSHIP BETWEEN PACKAGING LEVELS AND TEST
    7. 1.7 THE RELATIONSHIP BETWEEN DENSITY AND TEST
    8. 1.8 TEST GENERATION TECHNIQUES FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS
    9. 1.9 TEST GENERATION COSTS AND PROJECTIONS
    10. 1.10 BUILT-IN TEST AS THE SOLUTION TO TESTING VLSI DESIGNS
  8. 2: Introduction to Testable Design
    1. 2.1 AD HOC DESIGN TECHNIQUES
    2. 2.2 STRUCTURED DESIGN TECHNIQUES
    3. 2.3 BUILT-IN TEST
    4. 2.4 TESTABILITY MEASURES
  9. 3: Pseudorandom Sequence Generators
    1. 3.1 SHIFT-REGISTER IMPLEMENTATION OF A PSEUDORANDOM SEQUENCE
    2. 3.2 ANALYSIS OF SHIFT-REGISTER SEQUENCES
    3. 3.3 PERIODICITY OF SHIFT-REGISTER SEQUENCES
    4. 3.4 PRIMITIVE POLYNOMIALS
    5. 3.5 CHARACTERISTICS OF MAXIMUM-LENGTH LINEAR SHIFT-REGISTER SEQUENCES
    6. 3.6 LINEAR DEPENDENCIES IN m -SEQUENCES
  10. 4: Test Response Compression Techniques
    1. 4.1 ONES COUNT COMPRESSION
    2. 4.2 TRANSITION COUNT COMPRESSION
    3. 4.3 PARITY CHECK COMPRESSION
    4. 4.4 CYCLIC CODE COMPRESSION
    5. 4.5 SYNDROME TESTING
    6. 4.6 COMPRESSION USING WALSH SPECTRA
    7. 4.7 COMPARISONS
  11. 5: Shift Register Polynomial Division
    1. 5.1 POLYNOMIAL REPRESENTATION OF BINARY DATA
    2. 5.2 IMPLEMENTATION OF A CRC GENERATOR
    3. 5.3 ERROR POLYNOMIALS
    4. 5.4 ALTERNATIVE LFSR IMPLEMENTATION OF POLYNOMIAL DIVISION
    5. 5.5 VARIOUS FEEDBACK STRUCTURES
    6. 5.6 ALTERNATIVE DESCRIPTIONS OF SIGNATURE REGISTERS
    7. 5.7 MULTIPLE-INPUT SIGNATURE REGISTERS
    8. 5.8 MASKING IN MULTIPLE-INPUT SIGNATURE REGISTERS
    9. 5.9 MISR AS A SINGLE-INPUT SIGNATURE ANALYZER
    10. 5.10 RECIPROCAL POLYNOMIALS
    11. 5.11 WHAT POLYNOMIAL SHOULD BE USED FOR SIGNATURE ANALYSIS?
    12. 5.12 IMPROVING THE EFFECTIVENESS OF SIGNATURE ANALYSIS
    13. 5.13 SEQUENTIAL CIRCUITS
    14. 5.14 GENERATION OF THE GOOD MACHINE SIGNATURE
    15. 5.15 SUMMARY
  12. 6: Special Purpose Shift-Register Circuits
    1. 6.1 LINEAR FEEDBACK SHIFT REGISTERS
    2. 6.2 DE BRUIJN COUNTER
    3. 6.3 CONCATENATABLE LFSRS
    4. 6.4 k -CASCADE SEQUENCE GENERATORS
    5. 6.5 WEIGHTED PATTERN GENERATOR
    6. 6.6 TWO-DIMENSIONAL SEQUENCE GENERATORS
    7. 6.7 CONCLUSIONS
  13. 7: Random Pattern Built-in Test
    1. 7.1 RANDOM PATTERN TEST
    2. 7.2 ERROR LATENCY FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS
    3. 7.3 SIGNAL PROBABILITY COMPUTATION
    4. 7.4 DETECTION PROBABILITY CALCULATION
    5. 7.5 THE RANDOM PATTERN TEST LENGTH
    6. 7.6 WEIGHTED RANDOM PATTERNS
    7. 7.7 LOGIC MODIFICATION
    8. 7.8 RANDOM PATTERN TESTABILITY IN STRUCTURED DESIGNS
    9. 7.9 OTHER RANDOM PATTERN TESTABILITY EVALUATION METHODS
    10. 7.10 RANDOM PATTERN TESTING OF RANDOM ACCESS MEMORIES
    11. 7.11 FAULT PROPAGATION THROUGH RANDOM ACCESS MEMORIES
    12. 7.12 RANDOM PATTERN TESTABILITY OF DELAY FAULTS
    13. 7.13 TESTING FOR INTERMITTENT FAULTS
  14. 8: Built-in Test Structures
    1. 8.1 SCAN-PATH STRUCTURES
    2. 8.2 SPECIAL TOPICS IN BUILT-IN TEST STRUCTURES
    3. 8.3 BUILT-IN TEST STRUCTURES FROM OFF-THE-SHELF HARDWARE
  15. 9: Limitations of and Other Concerns Random Pattern Testing
    1. 9.1 INDETERMINATE STATES
    2. 9.2 SIMULTANEOUS SWITCHING
    3. 9.3 DRIVERS
    4. 9.4 TEST EFFECTIVENESS PROBLEMS
    5. 9.5 CIRCUIT RELIABILITY CONSIDERATIONS
    6. 9.6 PARAMETRIC TESTING
  16. 10: Test System Requirements for Built-in Test
    1. 10.1 TEST SYSTEM SUPPORT OF DIAGNOSIS
    2. 10.2 TEST SYSTEM SUPPORT OF PATH DELAY TEST
    3. 10.3 THE IDEAL TESTER
    4. 10.4 TEST SYSTEM SUPPORT OF FIELD TESTING
    5. 10.5 SOFTWARE FOR TESTER SUPPORT
  17. APPENDIX: A Primitive Polynomial for Every Degree through 300
  18. References
  19. Index