Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

CHAPTER 8

CROSSPOINT-BUFFERED SWITCHES

When more than one cell is contending for the limited link capacity inside a switch or at its outputs, buffers are provided to temporarily store the cells. Since the size of a buffer is finite, cells will be discarded when it is full. However, in previous chapters we have described several switch architectures with input buffering, output buffering (including shared memory), input and output buffering, and internal buffering in a multistage structure.

This chapter describes crosspoint-buffered switches, where each cross-point has a buffer. This switch architecture takes advantage of today's CMOS technology, where several millions of gates and several tens of millions of bits can be implemented on the same chip. Furthermore, there can be several hundred input and output signals operating at 2–3 Gbit/s on one chip. This switch architecture does not require any increase of the internal line speed. It eliminates the HOL blocking that occurs in the input-buffered switch, at the cost of having a large amount of crosspoint-buffer memory at each cross-point.

The remainder of this chapter is organized as follows. Section 8.1 describes a basic crosspoint-buffered switch architecture. The arbitration time among crosspoint buffers can become a bottleneck ...