Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

CHAPTER 4

SHARED-MEMORY SWITCHES

In shared-memory switches, all input and output ports have access to a common memory. In every cell time slot, all input ports can store incoming cells and all output ports can retrieve their outgoing cells (if any). A shared-memory switch works essentially as an output-buffered switch, and therefore also achieves the optimal throughput and delay performance. Furthermore, for a given cell loss rate, a shared-memory switch requires less buffers than other switches.

Because of centralized memory management to achieve buffer sharing, however, the switch size is limited by the memory read/write access time, within which N incoming and N outgoing cells in a time slot need to be accessed. As shown in the formula given below, the memory access cycle must be shorter than 1/2N of the cell slot, which is the transmission time of a cell on the link:

For instance, with a cell slot of 2.83 μs (53-byte cells at the line rate of 149.76 Mbit/s, or 155.52 Mbit/s × 26/27) and with a memory cycle time of 10 ns, the switch size is limited to 141.

Several commercial ATM switch systems based on the shared memory architecture provide a capacity of several tens of gigabits ...