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Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

Book Description

The effective design of high-speed, reliable switching systems is essential for moving the huge volumes of traffic and multimedia over modern communications networks. This book explains all the main packet-switching architectures, including all theoretical and practical topics relevant to the design and management of high-speed networks. Delivering the most systematic coverage available of the subject, the authors interweave fundamental concepts with real-world applications and include engineering case studies from wireless and fiber-optic communications.

Market: Hardware and Software Engineers in the telecommunication industry, System Engineers, and Technicians.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Contents
  5. PREFACE
    1. AUDIENCE
    2. ORGANIZATION OF THE BOOK
    3. ACKNOWLEDGMENTS
  6. CHAPTER 1: INTRODUCTION
    1. 1.1 ATM SWITCH SYSTEMS
    2. 1.2 IP ROUTER SYSTEMS
    3. 1.3 DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
    4. REFERENCES
  7. CHAPTER 2: BASICS OF PACKET SWITCHING
    1. 2.1 SWITCHING CONCEPTS
    2. 2.2 SWITCH ARCHITECTURE CLASSIFICATION
    3. 2.3 PERFORMANCE OF BASIC SWITCHES
    4. REFERENCES
  8. CHAPTER 3: INPUT-BUFFERED SWITCHES
    1. 3.1 A SIMPLE SWITCH MODEL
    2. 3.2 METHODS FOR IMPROVING PERFORMANCE
    3. 3.3 SCHEDULING ALGORITHMS
    4. 3.4 OUTPUT-QUEUING EMULATION
    5. 3.5 LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST ALGORITHM (LOOFA)
    6. REFERENCES
  9. CHAPTER 4: SHARED-MEMORY SWITCHES
    1. 4.1 LINKED LIST APPROACH
    2. 4.2 CONTENT-ADDRESSABLE MEMORY APPROACH
    3. 4.3 SPACE-TIME-SPACE APPROACH
    4. 4.4 MULTISTAGE SHARED-MEMORY SWITCHES
    5. 4.5 MULTICAST SHARED-MEMORY SWITCHES
    6. REFERENCES
  10. CHAPTER 5: BANYAN-BASED SWITCHES
    1. 5.1 BANYAN NETWORKS
    2. 5.2 BATCHER-SORTING NETWORK
    3. 5.3 OUTPUT CONTENTION RESOLUTION ALGORITHMS
    4. 5.4 THE SUNSHINE SWITCH
    5. 5.5 DEFLECTION ROUTING
    6. 5.6 MULTICAST COPY NETWORKS
    7. REFERENCES
  11. CHAPTER 6: KNOCKOUT-BASED SWITCHES
    1. 6.1 SINGLE-STAGE KNOCKOUT SWITCH
    2. 6.2 CHANNEL GROUPING PRINCIPLE
    3. 6.3 A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
    4. 6.4 A FAULT-TOLERANT MULTICAST OUTPUT-BUFFERED ATM SWITCH
    5. 6.5 APPENDIX
    6. REFERENCES
  12. CHAPTER 7: THE ABACUS SWITCH
    1. 7.1 BASIC ARCHITECTURE
    2. 7.2 MULTICAST CONTENTION RESOLUTION ALGORITHM
    3. 7.3 IMPLEMENTATION OF INPUT PORT CONTROLLER
    4. 7.4 PERFORMANCE
    5. 7.5 ATM ROUTING AND CONCENTRATION CHIP
    6. 7.6 ENHANCED ABACUS SWITCH
    7. 7.7 ABACUS SWITCH FOR PACKET SWITCHING
    8. REFERENCES
  13. CHAPTER 8: CROSSPOINT-BUFFERED SWITCHES
    1. 8.1 OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES
    2. 8.2 SCALABLE DISTRIBUTED-ARBITRATION SWITCH
    3. 8.3 MULTIPLE-QOS SDA SWITCH
    4. REFERENCES
  14. CHAPTER 9: THE TANDEM-CROSSPOINT SWITCH
    1. 9.1 OVERVIEW OF INPUT-OUTPUT-BUFFERED SWITCHES
    2. 9.2 TDXP STRUCTURE
    3. 9.3 PERFORMANCE OF TDXP SWITCH
    4. REFERENCES
  15. CHAPTER 10: CLOS-NETWORK SWITCHES
    1. 10.1 ROUTING PROPERTIES AND SCHEDULING METHODS
    2. 10.2 A SUBOPTIMAL STRAIGHT MATCHING METHOD FOR DYNAMIC ROUTING
    3. 10.3 THE ATLANTA SWITCH
    4. 10.4 THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
    5. 10.5 THE PATH SWITCH
    6. REFERENCES
  16. CHAPTER 11: OPTICAL PACKET SWITCHES
    1. 11.1 ALL-OPTICAL PACKET SWITCHES
    2. 11.2 OPTOELECTRONIC PACKET SWITCHES
    3. 11.3 THE 3M SWITCH
    4. 11.4 OPTICAL INTERCONNECTION NETWORK FOR TERABIT IP ROUTERS
    5. REFERENCES
  17. CHAPTER 12: WIRELESS ATM SWITCHES
    1. 12.1 WIRELESS ATM STRUCTURE OVERVIEWS
    2. 12.2 WIRELESS ATM SYSTEMS
    3. 12.3 RADIO ACCESS LAYERS
    4. 12.4 HANDOFF IN WIRELESS ATM
    5. 12.5 MOBILITY-SUPPORT ATM SWITCH
    6. REFERENCES
  18. CHAPTER 13: IP ROUTE LOOKUPS
    1. 13.1 IP ROUTER DESIGN
    2. 13.2 IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE
    3. 13.3 IP ROUTE LOOKUP BASED ON STANDARD TRIE STRUCTURE
    4. 13.4 PATRICIA TREE
    5. 13.5 SMALL FORWARDING TABLES FOR FAST ROUTE LOOKUPS
    6. 13.6 ROUTE LOOKUPS IN HARDWARE AT MEMORY ACCESS SPEEDS
    7. 13.7 IP LOOKUPS USING MULTIWAY SEARCH
    8. 13.8 IP ROUTE LOOKUPS FOR GIGABIT SWITCH ROUTERS
    9. 13.9 IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
    10. REFERENCES
  19. APPENDIX: SONET AND ATM PROTOCOLS
    1. A.1 ATM PROTOCOL REFERENCE MODEL
    2. A.2 SYNCHRONOUS OPTICAL NETWORK (SONET)
    3. A.3 SUBLAYER FUNCTIONS IN REFERENCE MODEL
    4. A.4 ASYNCHRONOUS TRANSFER MODE
    5. A.5 ATM ADAPTATION LAYER
    6. REFERENCES
  20. INDEX