Baseband Receiver Design for Wireless MIMO-OFDM Communications, 2nd Edition

Chapter 10

MIMO IC Design Examples

In MIMO circuit implementation, algorithms are developed by evaluating their error rate as well as their complexity. Thus, architectural design focuses on complexity reduction, pipeline design, and hardware utilization. Such algorithm and architecture co-design is crucial for IC implementation of MIMO-OFDM receivers.

10.1 Introduction

As introduced in the previous chapters, MIMO-OFDM receivers include sophisticated signal-processing algorithms, such as sphere decoding, turbo decoding, and iterative receivers. Unlike traditional communication systems design, in which algorithmic and hardware developments can be separated, currently, engineers must have knowledge of both algorithms and architectures to realize such intricate MIMO-OFDM baseband receivers. For algorithmic development, the performance of an algorithm can only be evaluated rigorously by actual implementation, especially from the complexity viewpoint. For example, the low-density parity-check (LDPC) decoders can be realized by using additions and comparisons, which seems simple. However, the main energy consumption of an LDPC decoder occurs in the memory access and complex interconnections among nodes, which can hardly be evaluated at the algorithmic level.

For hardware design, an energy-efficient and area-efficient integrated circuit (IC) can only be achieved by using “hardware-oriented algorithms,” which require several iterations between the hardware and algorithm design to ...