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Asynchronous Circuit Design by Chris J. Myers

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6

Muller Circuits

The infinite is the finite of every instant.

—Zen Saying

When I can't handle events, I let them handle themselves.

—Henry Ford

Life is pleasant. Death is peaceful. It's the transition that's troublesome.

—Isaac Asimov

We are ready for any unforeseen event that may or may not occur.

—Vice President Dan Quayle, 9/22/90

In this chapter we introduce the Muller school of thought to the synthesis of asynchronous circuits. Muller circuits are designed under the unbounded gate delay model. Under this model, circuits are guaranteed to work regardless of gate delays, assuming that wire delays are negligible. Muller circuit design requires explicit knowledge of the behaviors allowed by the environment. It does not, however, put any restriction on the speed of the environment.

The design of Muller circuits requires a somewhat different approach as compared with traditional sequential state machine design. Most synthesis methods for Muller circuits translate the higher-level specification into a state graph. Next, the state graph is examined to determine if a circuit can be generated using only the specified input and output signals. If two states are found that have the same values of inputs and outputs but lead through an output transition to different next states, no circuit can be produced directly. In this case, either the protocol must be changed or new internal state signals must be added to the design. The method of determining the needed state variables is quite different ...

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